G06F 30/3315
Using static timing analysis [sta]
Official title: using static timing analysis [STA]
G06F30/3315 (Using static timing analysis [sta]) appears on 379 US grants and 347 published applications in this corpus.
Search patents in G06F- Granted patents
- 379
- Published applications
- 347
- Assignees
- 107
- Inventors
- 833
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 1 | 0 |
| 2000 | 1 | 0 |
| 2001 | 2 | 0 |
| 2002 | 2 | 3 |
| 2003 | 2 | 6 |
| 2004 | 2 | 7 |
| 2005 | 2 | 4 |
| 2006 | 10 | 9 |
| 2007 | 4 | 6 |
| 2008 | 4 | 13 |
| 2009 | 11 | 9 |
| 2010 | 8 | 8 |
| 2011 | 13 | 10 |
| 2012 | 12 | 13 |
| 2013 | 25 | 22 |
| 2014 | 25 | 6 |
| 2015 | 11 | 22 |
| 2016 | 16 | 14 |
| 2017 | 23 | 18 |
| 2018 | 21 | 32 |
| 2019 | 42 | 19 |
| 2020 | 29 | 10 |
| 2021 | 24 | 21 |
| 2022 | 22 | 23 |
| 2023 | 19 | 28 |
| 2024 | 17 | 21 |
| 2025 | 17 | 12 |
| 2026 | 12 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method for determining performance of sequential logic elements and device8 Sep 2026US 12,730,952 B2Changxin Memory Technologies, Inc.
- Statistical timing characterization of superconducting electronic circuit designs8 Sep 2026US 12,730,954 B2Synopsys, Inc.
- Delay calculation with pattern matching for static timing analysis25 Aug 2026US 12,717,991 B2Synopsys, Inc.
- Timing optimization method and apparatus based on output transition constraints, and computer device7 Jul 2026US 12,675,623 B2Zhengxinyuan Technology (Hangzhou) Co., Ltd.
- Protecting against emission based side channel detection7 Jul 2026US 12,675,625 B2International Business Machines Corporation
- Method and system for exploring complex mega cells in integrated circuit8 Oct 2026US 2026/0310866 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Ai agent-based analysis of debugging reports for circuit design systems and applications8 Oct 2026US 2026/0310869 A1NVIDIA Corporation
- Dual-edge pulse modeling in circuit design testing23 Jul 2026US 2026/0212098 A1International Business Machines Corporation
- Generalized placement retiming for an integrated circuit design19 Mar 2026US 2026/0080139 A1International Business Machines Corporation
- Processing chip, design method, and electronic device19 Mar 2026US 2026/0081606 A1Huawei Technologies Co., Ltd.
Most cited
By later US patents
- Generation of engineering change order (ECO) constraints for use in selecting ECO repair techniques213US 7,454,731 B2Synopsys, Inc. · 2008
- Method, system, and program product for computing a yield gradient from statistical timing201US 7,480,880 B2International Business Machines Corporation · 2009
- Static timing analysis and dynamic simulation for custom and ASIC designs196US 7,590,953 B2Sage Software, Inc. · 2009
- Static timing analysis of semiconductor digital circuits136US 4,924,430 ATeradyne, Inc. · 1990
- Method for designing large standard-cell base integrated circuits117US 6,567,967 B2Monterey Design Systems, Inc. · 2003