Processing chip, design method, and electronic device

A design method for designing a processing chip, the method comprising:

• combining a first description file and a second description file to obtain a third description file, wherein the first description file describes a logical function of a first chip, wherein the first chip comprises a plurality of sub-circuits, wherein the plurality of sub-circuits are based on a same clock domain or one or more sub-circuits of the plurality of sub-circuits are based on different clock domains, wherein the second description file describes a logical function of an asynchronous clock interface circuit, and wherein the third description file is describes a logical function of the processing chip;
• performing timing constraint on the third description file;
• and
• obtaining a logic circuit structure of the processing chip based on the third description file on which timing constraint is performed;
• wherein the processing chip comprises a first sub-circuit, the asynchronous clock interface circuit, and a second sub-circuit, wherein the asynchronous clock interface circuit comprises a first beat conversion circuit, a first trigger circuit, and a second beat conversion circuit;
• wherein a first signal end of the first sub-circuit is coupled to a trigger input end of the first trigger circuit, wherein a trigger output end of the first trigger circuit is separately coupled to an input end of the first beat conversion circuit and an input end of the second beat conversion circuit, wherein an output end of the first beat conversion circuit is coupled to a third signal end of the first sub-circuit, and wherein an output end of the second beat conversion circuit is coupled to a second signal end of the second sub-circuit;
• and
• wherein a first clock output end of the first sub-circuit is coupled to a first clock end of the first beat conversion circuit, and wherein a second clock output end of the second sub-circuit is coupled to a second clock end of the second beat conversion circuit.

An electronic device, comprising:

• a circuit board;
• and
• a processing chip disposed on the circuit board, wherein the processing chip compress a first sub-circuit, an asynchronous clock interface circuit, and a second sub-circuit, wherein the asynchronous clock interface circuit comprises a first beat conversion circuit, a first trigger circuit, and a second beat conversion circuit;
• wherein a first signal end of the first sub-circuit is coupled to a trigger input end of the first trigger circuit, wherein a trigger output end of the first trigger circuit is separately coupled to an input end of the first beat conversion circuit and an input end of the second beat conversion circuit, wherein an output end of the first beat conversion circuit is coupled to a third signal end of the first sub-circuit, and wherein an output end of the second beat conversion circuit is coupled to a second signal end of the second sub-circuit;
• and
• wherein a first clock output end of the first sub-circuit is coupled to a first clock end of the first beat conversion circuit, and wherein a second clock output end of the second sub-circuit is coupled to a second clock end of the second beat conversion circuit.