US 4,924,430 AGranted

Static timing analysis of semiconductor digital circuits

AssigneeTeradyne, Inc.

InventorsJohn J. Zasio, Kenneth C. Choy, Darrell R. Parham

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Abstract

The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.

Claims11

Dependent claims

A method of verifying time-oriented operating requirements of a logic circuit including logic elements that are to be fabricated as semiconductor circuits to operate with propagation delays therethrough on applied data and clock signals that are correlated within predetermined ranges of timing parameters, the method comprising the steps of:

designating for each of the logic elements the absolute fast and relative slow extremes of one range of propagation delays therethrough;
designating for each of said logic elements the relative fast and absolute slow extremes of another range of propagation delays therethrough;
tracing selected data signal paths including logic elements through the logic circuit;
tracing selected clock signal paths through the logic circuit to selected logic elements;
accumulating the propagation delays at said absolute fast, relative slow, relative fast and absolute slow extremes of said ranges for logic elements along both the selected clock path and data signal path;
comparing the accumulated absolute fast path values to the relative slow path values of one range of propagation delays of the respective clock and data paths through the selected logic elements to determine the correlation of said absolute fast path values and said relative slow path values within a predetermined range of timing parameters;
and
comparing the accumulated relative fast path values to the absolute slow path values of another range of propagation delays of the respective clock and data paths through the selected logic elements to determine the correlation of said relative fast path values and said absolute slow path values within a predetermined range of timing parameters.

5 more elements

A method of verifying time-oriented operating requirements of a logic circuit including logic elements that are to be fabricated as semiconductor circuits to operate within a plurality of ranges of propagation delays therethrough on applied first and second signals that are correlated within predetermined ranges of timing parameters, the method comprising the steps of:

designating for each of the logic elements at least four extremes of propagation delays therethrough including absolute slow and relative fast and absolute fast and relative slow;
tracing selected first signal paths including logic elements through the logic circuit;
tracing selected second signal paths through the logic circuit to selected logic elements;
selectively accumulating the propagation delays at both absolute and relative extremes of ranges for each logic element along the selected first signal path;
selectively accumulating the propagation delays at both absolute and relative extremes of ranges for each logic element along the selected second signal path to the selected logic element;
and
comparing the accumulated absolute slow and relative slow values of first signal propagation delays along the selected first signal path to the selected logic element with the accumulated respective relative fast and absolute fast values of second signal propagation delays along the selected second signal path to the selected logic element for correlation of respective accumulated absolute and relative values within each of the predetermined ranges of timing parameters for said logic element.

4 more elements

Dependencies are inferred from the claim text.