Generalized placement retiming for an integrated circuit design

A method for rewriting a netlist to enlarge a size of a retimeable region, the method comprising:

• identifying a fanout-free logic cone including gates at a boundary between the retimeable region and an unretimeable region;
• determining, for the fanout-free logic cone, an equivalent alternative sub-function including as many leaves as possible from the retimeable region and no leaves from the unretimeable region;
• and
• responsive to the sub-function including more leaves in the retimeable region than the fanout-free logic cone, rewriting the netlist to include the sub-function.

A computer program product, comprising:

• a storage device;
• and
• program code stored within the storage device and executable by processing circuitry of a data processing system to cause the data processing system to perform min-cut based retiming of a netlist, wherein min-cut based retiming of the netlist includes:
• based on a netlist of a circuit design, forming a min-cut based retiming graph, wherein forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph;
• computing a min-cut of the circuit design based on the min-cut based retiming graph, wherein the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph;
• and
• based on the min-cut, forming a behaviorally equivalent retimed netlist, including in the particular region.

A computer program product, comprising:

• a storage device;
• and
• program code stored within the storage device and executable by processing circuitry of a data processing system to cause the data processing system to perform rewriting a netlist to enlarge a size of a retimeable region, wherein rewriting the netlist includes:
• identifying a fanout-free logic cone including gates at a boundary between the retimeable region and an unretimeable region;
• determining, for the fanout-free logic cone, an equivalent alternative sub-function including as many leaves as possible from the retimeable region and no leaves from the unretimeable region;
• and
• responsive to the sub-function including more leaves in the retimeable region than the fanout-free logic cone, rewriting the netlist to include the sub-function.

A data processing system, comprising:

• processing circuitry;
• and
• a storage device coupled to the processor set, wherein the storage device includes program code executable by the processing circuitry to cause the data processing system to perform:
• based on a netlist of a circuit design, forming a min-cut based retiming graph, wherein forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph;
• computing a min-cut of the circuit design based on the min-cut based retiming graph, wherein the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph;
• and
• based on the min-cut, forming a behaviorally equivalent retimed netlist, including in the particular region.