Statistical timing characterization of superconducting electronic circuit designs

A method for generating a timing library for a superconducting electronic circuit design, the method comprising:

• determining a condition that indicates whether a superconducting electronic circuit design passes or fails logic verification;
• determining, according to the condition and by a processor, an edge-of-failure value for a timing parameter for the superconducting electronic circuit design;
• simulating, by the processor, the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a first process variation to produce a first timing value for the superconducting electronic circuit design;
• simulating, by the processor, the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a second process variation to produce a second timing value for the superconducting electronic circuit design;
• and
• generating a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.

A non-transitory computer readable medium storing instructions for generating a timing library for a superconducting electronic circuit design, wherein when the instructions are executed by a processor, the processor:

• determines, based on a condition indicating whether a superconducting electronic circuit design passes or fails logic verification, an edge-of-failure value for a timing parameter for the superconducting electronic circuit design;
• simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a plurality of process variations to produce a plurality of timing values for the superconducting electronic circuit design;
• and
• generates a timing library for the superconducting electronic circuit design based on the plurality of timing values.