Delay calculation with pattern matching for static timing analysis
AssigneeSynopsys, Inc.
InventorsPeivand Tehrani, Chenwei Dustin Liu, Ahmed Shebaita
Life of this patent
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Abstract
A method of performing static timing analysis for a circuit design includes, in part, identifying a multitude of logic blocks of the circuit design matching a design pattern; determining values of a multitude of electrical properties associated with a first logic block representative of each of the plurality of logic blocks; and determining, during the static timing analysis, a delay associated with each of the multitude of logic blocks using the values of the electrical properties.
Claims18
A method of performing static timing analysis for a circuit design, the method comprising:
- identifying a plurality of logic blocks of the circuit design matching a design pattern, each matching logic block having an instantiation of at least a first logic gate driving an instantiation of at least a second logic gate wherein a time constant associated with parasitics of a net coupling the at least first logic gate to the at least second logic gate is smaller than a threshold value,
- determining values of a plurality of electrical properties associated with a first logic block representative of each of the plurality of logic blocks;
- and
- determining, during the static timing analysis, a delay associated with each of the plurality of logic blocks using the values of the electrical properties.
A system comprising:
- a memory storing instructions;
- and
- a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
- identify a plurality of logic blocks of the circuit design matching a design pattern, each matching logic block having an instantiation of at least a first logic gate driving an instantiation of at least a second logic gate wherein a time constant associated with parasitics of a net coupling the at least first logic gate to the at least second logic gate is smaller than a threshold value;
- determine values of a plurality of electrical properties associated with a first logic block representative of each of the plurality of logic blocks;
- and
- determine, during the static timing analysis, a delay associated with each of the plurality of logic blocks using the values of the electrical properties.
A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
- identify a plurality of logic blocks of the circuit matching a design pattern, each logic block having an instantiation of at least a first logic gate driving an instantiation of at least a second logic gate;
- determine k*l*m delays associated with a first logic block representative of each of the plurality of logic blocks, wherein k represents a number of loads seen by the at least first logic gate instantiated in the first logic block, l represents a number of normalized loads seen by the at least second logic gate instantiated in the first logic block, and m represents a number of slew rates associated with waveforms applied to the first logic block;
- store the k*l*m delay values in a database;
- and
- determine a delay for each of the plurality of logic blocks by interpolating between the stored delay values and in accordance with a load seen by the at least first logic gate instantiated in the logic block, a normalized load seen by the at least second logic gate instantiated in the logic block, and a waveform applied to the logic block, wherein each of k, l, and m is an integer greater than or equal to 2.
Dependencies are inferred from the claim text.