Method for designing large standard-cell base integrated circuits
AssigneeMonterey Design Systems, Inc.
InventorsYaacov I. Greidinger, David S. Reed, Ara Markosian, Stephen P. Sample, Jonathan A. Frankle, Hasmik Lazaryan
Life of this patent
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Abstract
An automated method of designing large digital integrated circuits using a software program to partition the design into physically realizable blocks and then create the connections between blocks so as to maximize operating speed and routability while minimizing the area of the resulting integrated circuit. Timing and physical constraints are generated for each physically realizable block so that standard-cell place and route software can create each block independently as if it were a separate integrated circuit.
Claims36
A method for physically designing an integrated circuit comprising:
- importing a netlist description of an integrated circuit design, said netlist description comprising a plurality of hierarchical arranged branches;
- selecting atomic blocks for each of said plurality of hierarchically arranged branches, each of said atomic blocks selected to be one or more hierarchy levels above the bottom of a corresponding one of said hierarchically arranged branches, each of said atomic blocks being either an atomic hard block, an atomic soft block or an atomic hierarchical block;
- flattening each of said plurality of hierarchically arranged branches by eliminating superfluous levels of hierarchy above said atomic blocks;
- partitioning each of said atomic blocks into one of a plurality of place and route units (“PRUs”);
- and
- positioning said atomic blocks within each of said plurality of PRUs.
A method of routing an integrated circuit design comprised of a plurality of place and route units (“PRUs”), comprising:
- creating dummy ports on each of said PRUs, said dummy ports allowing a net to traverse from a first of said plurality of PRUs to a second of said plurality of PRUs;
- connecting said dummy ports on said PRUs by routing nets between them;
- determining where said routing nets cross edges of said plurality of PRUs;
- deleting said dummy ports;
- and
- generating real ports where said routing nets cross edges of said plurality of PRUs.
A method of fitting an integrated circuit design within a predefined area, the integrated circuit design comprising one or more of hard blocks, hierarchical blocks and soft blocks, the hard blocks having a fixed shape, comprising:
- determining optimal placement of each of the hard blocks, if any, within the predefined area;
- and
- selecting a rectilinear shape for each of the soft blocks, if any, and hierarchical blocks, if any, so that the soft blocks, if any, and hierarchical blocks, if any, fit within spaces of the predefined area left unoccupied by the hard blocks.
A method of fitting an integrated circuit design within a predefined area, said method comprising:
- determining placement of at least one hard block within the predefined area, wherein said at least one hard block has a predefined shape;
- and
- selecting a rectilinear shape for at least one block within the predefined area, such that said at least one block fits within space in said predefined area left unoccupied by said at least one hard block.
Dependencies are inferred from the claim text.