G06F 30/3312
Timing analysis
G06F30/3312 (Timing analysis) appears on 2,020 US grants and 1,654 published applications in this corpus.
Search patents in G06F- Granted patents
- 2,020
- Published applications
- 1,654
- Assignees
- 346
- Inventors
- 3,404
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 4 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 5 | 0 |
| 1994 | 3 | 0 |
| 1995 | 6 | 0 |
| 1996 | 11 | 0 |
| 1997 | 16 | 0 |
| 1998 | 21 | 0 |
| 1999 | 22 | 0 |
| 2000 | 15 | 0 |
| 2001 | 18 | 4 |
| 2002 | 18 | 11 |
| 2003 | 29 | 32 |
| 2004 | 30 | 44 |
| 2005 | 34 | 62 |
| 2006 | 59 | 82 |
| 2007 | 69 | 73 |
| 2008 | 67 | 115 |
| 2009 | 67 | 117 |
| 2010 | 100 | 70 |
| 2011 | 119 | 65 |
| 2012 | 105 | 75 |
| 2013 | 134 | 76 |
| 2014 | 121 | 60 |
| 2015 | 74 | 88 |
| 2016 | 86 | 87 |
| 2017 | 120 | 97 |
| 2018 | 85 | 112 |
| 2019 | 151 | 67 |
| 2020 | 140 | 66 |
| 2021 | 82 | 51 |
| 2022 | 52 | 34 |
| 2023 | 43 | 48 |
| 2024 | 34 | 52 |
| 2025 | 47 | 39 |
| 2026 | 29 | 27 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method for determining performance of sequential logic elements and device8 Sep 2026US 12,730,952 B2Changxin Memory Technologies, Inc.
- Techniques for monitoring digital timing margins25 Aug 2026US 12,717,394 B2Arm Limited
- Delay calculation with pattern matching for static timing analysis25 Aug 2026US 12,717,991 B2Synopsys, Inc.
- Retiming sequential elements having initital states11 Aug 2026US 12,705,410 B2Xilinx, Inc.
- Unified framework and method for accurate context-aware timing modeling4 Aug 2026US 12,699,828 B2Synopsys, Inc.
- Circuit design method and electronic device executing circuit design method10 Sep 2026US 2026/0268054 A1Realtek Semiconductor Corp.
- Ir optimization technique of integrated circuit layout13 Aug 2026US 2026/0236656 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Adapting design constraints for static timing analysis of a circuit30 Jul 2026US 2026/0220350 A1International Business Machines Corporation
- Dual-edge pulse modeling in circuit design testing23 Jul 2026US 2026/0212098 A1International Business Machines Corporation
- System and method for predicting power consumption of integrated circuit and method for designing integrated circuit using the same9 Jul 2026US 2026/0195514 A1SK hynix Inc.
Most cited
By later US patents
- Deep sub-micron static timing analysis in the presence of crosstalk244US 6,405,348 B1Synopsys, Inc. · 2002
- Frequency driven layout and method for field programmable gate arrays239US 5,659,484 AXilinx, Inc. · 1997
- Robust calculation of crosstalk delay change in integrated circuit design220US 7,359,843 B1Cadence Design Systems, Inc. · 2008
- Systems, methods, and apparatus to perform statistical static timing analysis220US 7,487,475 B1Cadence Design Systems, Inc. · 2009
- Split and merge design flow concept for fast turnaround time of circuit layout design216US 6,898,770 B2LSI Logic Corporation · 2005