Systems, methods, and apparatus to perform statistical static timing analysis
AssigneeCadence Design Systems, Inc.
InventorsHarish Kriplani, Shiang-Tang Huang
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Abstract
A method and an apparatus to perform statistical static timing analysis have been disclosed. In one embodiment, the method includes performing statistical analysis on performance data of a circuit from a plurality of libraries at two or more process corners using a static timing analysis module, and estimating performance of the circuit at a predetermined confidence level based on results of the statistical analysis during an automated design flow of the circuit without using libraries at the predetermined confidence level.
Claims23
A method of automated design flow of a circuit, the method comprising:
- performing statistical static analysis on performance data of a circuit from a plurality of device libraries at a respective plurality of process corners using a static timing analysis module, each device library having a library confidence level;
- and
- estimating performance of the circuit at a predetermined confidence level based on results of the statistical static analysis without forming a device library having the predetermined confidence level,
- wherein the predetermined confidence level is a user specified confidence level that differs from each library confidence level of the plurality of device libraries.
A machine-readable storage device that provides instructions that, if executed by a computer, will perform operations comprising:
- performing statistical static analysis on performance data of a circuit from a plurality of device libraries at a respective plurality of process corners using a static timing analysis module, each device library having a library confidence level;
- and
- estimating performance of the circuit at a predetermined confidence level based on results of the statistical static analysis without forming a device library having the predetermined confidence level,
- wherein the predetermined confidence level is a user specified confidence level that differs from each library confidence level of the plurality of device libraries.
A system comprising:
- a processor;
- and
- a memory to store instructions, the instructions when executed by the processor will perform operations comprising:
- performing statistical static analysis on performance data of a circuit from a plurality of device libraries at a respective plurality of process corners using a static timing analysis module, each device library having a library confidence level;
- and
- estimating performance of the circuit at a predetermined confidence level based on results of the statistical static analysis without forming a device library having the predetermined confidence level,
- wherein the predetermined confidence level is a user specified confidence level that differs from each library confidence level of the plurality of device libraries.
Dependencies are inferred from the claim text.