Robust calculation of crosstalk delay change in integrated circuit design
AssigneeCadence Design Systems, Inc.
InventorsIgor Keller, Kenneth Tseng, Nishath Verghese
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Abstract
A method of delay change determination in an integrated circuit design including a stage with a victim net and one or more aggressor nets capacitively coupled thereto, the method comprising: determining a nominal (noiseless) victim net signal transition; determining a noisy victim net signal transition; and determining a delay change based upon nominal and noisy victim signal transition arrival times at a victim net receiver output.
Claims56
A computer implemented method of determining aggressor-induced delay change in a victim net of a stage of an integrated circuit design, the stage including a victim net driver gate, a receiver gate and an interconnect network including a victim net and an aggressor net, comprising:
- providing an input and output voltage dependent current model of the victim net driver gate;
- producing a model of a load presented to an output of the driver gate by the interconnect network;
- producing a model of the interconnect network of the stage, which can be used to propagate a waveform from an output of the driver gate to an input of the receiver gate;
- simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,
- providing a signal transition at an input of the driver gate;
- using the current model of the driver gate and the load model of the interconnect network to produce a nominal driver gate output waveform resulting from the provided input signal transition;
- and
- using the interconnect model to propagate the nominal driver gate output waveform from the driver gate output to the receiver gate input;
- simulating behavior of the victim net during noisy transition by performing steps including,
- providing a signal transition at an input of the driver gate;
- providing an aggressor-induced current waveform to an output of the driver gate;
- using the current model of the driver gate and the load model of the interconnect network to produce a noisy driver gate output waveform resulting from the provided input signal transition and the aggressor-induced current waveform;
- and
- using the interconnect model to propagate the noisy driver gate output waveform from the driver gate output to the receiver gate input;
- providing an aggressor-induced voltage waveform to an input of the receiver gate;
- producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition;
- and
- saving the produced value in computer readable memory.
An article of manufacture including a computer readable medium encoded with an information structure representing a driver circuit, the information structure comprising:
- a current model that associates instantaneous values of input node voltage, output node voltage and output node current of the driver circuit;
- a model of capacitance between an input node and an output node of the driver circuit;
- and
- a model of capacitance between the output node of the driver circuit and a ground potential;
- wherein the information structure is operable to cause a computer to associate current drawn by the driver circuit output node in response to voltages applied to the driver circuit input and output nodes.
An article of manufacture including a computer readable medium encoded with an information structure representing a driver circuit, the information structure comprising:
- a current model that associates instantaneous values of driver circuit input node voltage, driver circuit output node voltage and driver circuit output node current;
- a model of miller capacitance of the output node of the driver circuit;
- and
- a model of ground capacitance of the output node of the driver circuit;
- wherein the information structure is operable to cause a computer to associate current drawn by the driver circuit output node in response to voltages applied to the driver circuit input and output nodes.
An article of manufacture including a computer readable medium encoded with computer instructions to cause the computer to perform a circuit simulation process comprising the steps of:
- for each of a plurality of different pairs of first and second DC voltage values,
- sensitizing an input node of a cell model of the driver circuit with a first DC voltage value;
- sensitizing an output node of the cell model with a second DC voltage value;
- generating a value of current drawn by the output node of the cell model based upon the provided first DC voltage value and the provided second DC voltage value;
- and
- saving the generated value in computer readable memory.
An article of manufacture including a computer readable medium encoded with a current model of a driver circuit, the current model operable to cause the computer to associate input voltage values, output voltage values and current values, the current model produced by a process including the steps of:
- for each of a plurality of different pairs of first and second DC voltage values,
- sensitizing an input node of a cell model representing the driver circuit with a first DC voltage value;
- sensitizing an output node of the cell model with a second DC voltage value;
- and
- generating a value of current drawn by the output node of the cell model based upon the provided first DC voltage value and the provided second DC voltage value.
An article of manufacture including a computer readable medium encoded with instructions to cause the computer to perform a method of simulating aggressor-induced behavior of a driver circuit and an interconnect network driven by the driver circuit, the method comprising:
- providing a voltage signal transition on an input of a current model representing the driver circuit, the current model associating instantaneous values of input voltage, output voltage and output current of the driver circuit;
- providing an aggressor induced current waveform on a node interconnecting an output of the current model and a load model representing the interconnect network, the load model approximating output point admittance of the interconnect network;
- and
- using the current model and the load model to produce a voltage waveform on the output of the current model based upon the received input voltage signal transition and the received aggressor induced waveform;
- wherein the voltage waveform represents a voltage transition on the driver circuit output.
A computer implemented method of determining aggressor-induced delay change in a victim net in an integrated circuit design, the victim net including a driver circuit and an interconnect network between the driver circuit and a receiver circuit, the method comprising:
- simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,
- providing a voltage signal transition on an input of the driver circuit;
- using a driver circuit current model and a load model approximating output point admittance of the interconnect network presented to an output of the driver circuit, to produce a nominal driver circuit output voltage waveform resulting from the provided transition signal;
- and
- using a computational model of the interconnect network to propagate the nominal driver circuit output voltage waveform to an input of the receiver circuit;
- simulating behavior of the victim net during noisy transition by performing steps including,
- providing a voltage signal transition on the input of the driver circuit;
- providing an aggressor induced current waveform to the output node of the driver circuit;
- using the driver circuit current model and the load model to produce a noisy driver circuit output voltage waveform resulting from the provided transition signal and the aggressor-induced current waveform;
- and
- using the computational model of the interconnect network to propagate the noisy output voltage waveform to an input of the receiver circuit;
- producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition;
- and
- saving the produced value in computer readable memory.
An article of manufacture including a computer readable medium encoded with instructions to cause the computer to perform a method of determining aggressor-induced delay change in a victim net of a stage of an integrated circuit design, the stage including a victim net driver gate, a receiver gate and an interconnect network including a victim net and an aggressor net, the method comprising:
- simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,
- providing a signal transition to an input of the driver gate;
- using a current model of the driver gate and a load model of the interconnect network to produce a nominal driver gate output waveform resulting from the provided input signal transition;
- and
- using a model of the interconnect network to propagate the nominal driver gate output waveform from the driver gate output to the receiver gate input;
- simulating behavior of the victim net during noisy transition by performing steps including,
- providing a signal transition at the input of the driver gate;
- providing at least one aggressor-induced current waveform to an output of the driver gate;
- using the current model of the driver gate and the load model of the interconnect network to produce a noisy driver gate output waveform resulting from the provided input signal transition and the at least one aggressor-induced current waveform provided to the driver gate output;
- and
- using the interconnect model to propagate the noisy driver gate output waveform from the driver gate output to the receiver gate input;
- providing at least one aggressor-induced voltage waveform to an input of the receiver gate;
- producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition;
- and
- saving the produced value to computer readable memory.
An article of manufacture including a computer readable medium encoded with instructions to cause the computer to perform a method of determining aggressor-induced delay change in a victim net of a stage of an integrated circuit design, the stage including a victim net driver gate, a receiver gate and an interconnect network including the victim net and an aggressor net, the method comprising:
- simulating behavior of the victim net during nominal (noiseless) transition by performing steps including,
- providing a voltage signal transition on an input of a the driver gate;
- using a current model of the driver gate and a load model representing the interconnect network, the load model approximating output point admittance of the interconnect network, to produce a nominal driver gate output voltage waveform in response to the input voltage transition;
- and
- using a computational model of the interconnect network to propagate the nominal driver gate output voltage waveform to an input of the receiver gate;
- simulating behavior of the victim net during noisy transition by performing steps including,
- providing a voltage signal transition to the input of the driver gate;
- providing an aggressor induced current waveform to an output of the driver gate;
- using the current model of the driver gate and the load model to produce a noisy driver gate output voltage waveform in response to the input voltage transition and the aggressor induced current waveform;
- and
- using the computational model of the interconnect network to propagate the noisy driver gate output voltage waveform to an input of the receiver gate;
- producing a value representing a difference between delay associated with the simulated noiseless transition and delay associated with the simulated noisy transition;
- and
- saving the produced value to computer readable memory.
Dependencies are inferred from the claim text.