Adapting design constraints for static timing analysis of a circuit

A computer system comprising:

• a processor set;
• one or more computer-readable storage media;
• and
• program instructions stored on the one or more computer-readable storage media to cause the processor set to perform operations comprising:
• receiving a set of prior constraints associated with a prior clock schema for the circuit;
• receiving an indication of a desired clock schema for the circuit;
• receiving transformation specifications for the circuit and a design topology for the circuit;
• analyzing the set of prior constraints, the prior clock schema, the desired clock schema, the transformation specifications, and the design topology to determine a set of new constraints for the desired clock schema for the circuit;
• and
• causing the circuit to be fabricated based at least in part on the set of new constraints for the desired clock schema for the circuit.

A computer program product comprising:

• one or more computer-readable storage media;
• and
• program instructions stored on the one or more computer-readable storage media to perform operations comprising:
• receiving a set of prior constraints associated with a prior clock schema for the circuit;
• receiving an indication of a desired clock schema for the circuit;
• receiving transformation specifications for the circuit and a design topology for the circuit;
• analyzing the set of prior constraints, the prior clock schema, the desired clock schema, the transformation specifications, and the design topology to determine a set of new constraints for the desired clock schema for the circuit;
• and
• causing the circuit to be fabricated based at least in part on the set of new constraints for the desired clock schema for the circuit.