G06F 2115/06
Structured asics
Official title: Structured ASICs
G06F2115/06 (Structured asics) appears on 125 US grants and 118 published applications in this corpus.
Search patents in G06F- Granted patents
- 125
- Published applications
- 118
- Assignees
- 67
- Inventors
- 314
- Latest grant
- 21 Apr 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2000 | 1 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 1 | 4 |
| 2005 | 2 | 9 |
| 2006 | 3 | 5 |
| 2007 | 6 | 4 |
| 2008 | 6 | 2 |
| 2009 | 4 | 2 |
| 2010 | 3 | 4 |
| 2011 | 6 | 1 |
| 2012 | 4 | 2 |
| 2013 | 3 | 1 |
| 2014 | 5 | 1 |
| 2015 | 7 | 8 |
| 2016 | 7 | 4 |
| 2017 | 6 | 6 |
| 2018 | 2 | 6 |
| 2019 | 13 | 9 |
| 2020 | 9 | 10 |
| 2021 | 9 | 6 |
| 2022 | 6 | 9 |
| 2023 | 7 | 8 |
| 2024 | 5 | 9 |
| 2025 | 6 | 6 |
| 2026 | 4 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization21 Apr 2026US 12,608,523 B1Synopsys, Inc.
- Integrated circuit generation with improved interconnect31 Mar 2026US 12,591,527 B2SiFive, Inc.
- Digital circuit board map for monitoring integrated circuit chips10 Feb 2026US 12,547,807 B1Auradine, Inc.
- Method and apparatus for checking signal line10 Feb 2026US 12,547,812 B2Changxin Memory Technologies, Inc.
- Power envelope analysis for the thermal optimization of multi-chip modules4 Nov 2025US 12,462,084 B2STATS ChipPAC Pte. Ltd.
- Process technology computer aided design with improved after-etching inspection modleing17 Sep 2026US 2026/0278227 A1Taiwan Semiconductor Manufacturing Company.Ltd
- System and method for predicting power consumption of integrated circuit and method for designing integrated circuit using the same9 Jul 2026US 2026/0195514 A1SK hynix Inc.
- Post-Routing Congestion Optimization11 Sep 2025US 2025/0284873 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Three-dimensional integrated circuit (3dic) and 3dic design method and system28 Aug 2025US 2025/0272465 A1GLOBALFOUNDRIES U. S. Inc.
- Methods of generating hardware description language (hdl)8 May 2025US 2025/0148178 A1Triad Semiconductor, Inc.
Most cited
By later US patents
- Three dimensional memory in a system on a chip499US 8,042,082 B22011
- Structured ASIC device with configurable die size and selectable embedded functions262US 7,337,425 B2AMI Semiconductor, Inc. · 2008
- Basic cell architecture for structured application-specific integrated circuits122US 7,404,154 B1LSI Corporation · 2008
- MPGA products based on a prototype FPGA111US 7,673,273 B2Tier Logic, Inc. · 2010
- Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost88US 8,667,439 B1NetSpeed Systems · 2014