Integrated circuit generation with improved interconnect

A method comprising:

• propagating metadata associated with at least a first transaction source to be associated with at least a first address decoder, wherein the first address decoder is configured to be connected to a cache and the metadata indicates cacheability of at least one memory address associated with the first transaction source, and wherein an integrated circuit design includes a hardware construction language expression of the first transaction source, the first address decoder, and the cache;
• and
• compiling the integrated circuit design to produce a design output based on the metadata, wherein the design output includes an instance of the first address decoder configured to transmit memory transactions to circuitry that bypasses the cache for memory locations having the metadata indicating that such memory locations are not cacheable, and wherein the first address decoder is further configured to transmit memory transactions to the cache along a separate cache path for memory locations having metadata indicating that such memory locations are cacheable.

A method comprising:

• accessing design parameters to configure an integrated circuit design, wherein the integrated circuit design includes a plurality of processing nodes to be included in an integrated circuit, wherein a processing node is configured to transmit a plurality of memory transactions to memory addresses;
• and
• compiling the integrated circuit design to generate a design output including a first transaction router and a second transaction router, wherein the first transaction router receives memory transactions from the plurality of processing nodes and determines whether a memory transaction is targeting a cacheable memory address, separates the memory transactions based on whether a memory transaction targets a cacheable memory address or a non-cacheable memory address, and routes memory transactions targeting the non-cacheable memory address to a non-cache path, and wherein the second transaction router receives memory transactions targeting cacheable memory addresses from the first transaction router and routes the memory transactions targeting cacheable memory addresses through a bus interface associated with cache addresses.