Method and apparatus for checking signal line

An apparatus for checking a signal line in a circuit layout, comprising at least one processor and a memory, wherein the memory stores computer executable instructions, and the at least one processor executes the computer executable instructions to:

• obtain custom design information of a target signal line in a circuit schematic, and generate a layout design rule corresponding to the target signal line based on the custom design information;
• generate the circuit layout based on the circuit schematic, and add a third label to a position of the target signal line in the circuit layout, wherein the third label comprises the custom design information corresponding to the target signal line obtained from the circuit schematic;
• check whether the target signal line meets the layout design rule;
• add a first label to the position of the target signal line in the circuit layout in response to the target signal line in the circuit layout not meeting the layout design rule, wherein the first label is configured to indicate that the target signal line does not meet the layout design rule;
• and
• modify the target signal line in the circuit layout based on the third label added to the position of the target signal line in the circuit layout until the target signal line in the circuit layout meets the layout design rule.

A non-transitory computer-readable storage medium configured with computer executable instructions, wherein upon being executed by one or more processors, the instructions cause the one or more processors to perform operations for checking a signal line in a circuit layout, the operations comprise:

• obtaining custom design information of a target signal line in a circuit schematic, and generating a layout design rule corresponding to the target signal line based on the custom design information;
• generating the circuit layout based on the circuit schematic, and adding a third label to a position of the target signal line in the circuit layout, wherein the third label comprises the custom design information corresponding to the target signal line obtained from the circuit schematic;
• checking whether the target signal line meets the layout design rule;
• and
• adding a first label to the position of the target signal line in the circuit layout in response to the target signal line in the circuit layout not meeting the layout design rule, wherein the first label is configured to indicate that the target signal line does not meet the layout design rule, wherein after adding the first label to the position of the target signal line in the circuit layout, the operations performed by the one or more processors further comprises:
• modifying the target signal line in the circuit layout based on the third label added to the position of the target signal line in the circuit layout until the target signal line in the circuit layout meets the layout design rule.