US 8,667,439 B1 · Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Abstract

Systems and methods described herein are directed to solutions for Network on Chip (NoC) interconnects that automatically and dynamically determines the position of various hosts in a NoC topology based on the connectivity, bandwidth and latency requirements of the system traffic flows and certain performance optimization metrics such as system interconnect latency and interconnect cost. The example implementations selects hosts for relocation consideration and determines a new possible position for them in the NoC based on the system traffic specification, and using probabilistic functions to decide if the relocation is carried out or not. The procedure is repeated over new sets of hosts until certain optimization targets are satisfied or repetition count is exceeded.

Claims21

Dependent claims

A method for determining host positions for a Network-on-Chip (NoC) topology, comprising:

utilizing a processor to:
select, from a plurality of hosts of the NoC topology, a first host based on a weight assigned to the first host;
select a location from a plurality of locations that neighbors a second host from the plurality of hosts of the NoC topology, the second host determined from at least one probability assigned to at least one of the plurality of hosts from a first probabilistic acceptance function, based on at least one probability assigned to at least one of the plurality of locations that neighbors the second host from a second probabilistic acceptance function;
and
move the first host to the location for a relocation decision based on a third probabilistic acceptance function that is a result indicative of accepting the moving of the first host.

2 more elements

A non-transitory computer readable storage medium storing instructions for causing a computer to determine host positions for a Network-on-Chip (NoC) topology, the instructions comprising:

selecting, from a plurality of hosts of the NoC topology, a first host based on a weight assigned to the first host;
selecting a location from a plurality of locations that neighbors a second host from the plurality of hosts of the NoC topology, the second host determined from at least one probability assigned to at least one of the plurality of hosts from a first probabilistic acceptance function, based on at least one probability assigned to at least one of the plurality of locations that neighbors the second host from a second probabilistic acceptance function;
and
moving the first host to the location for a relocation decision based on a third probabilistic acceptance function that is a result indicative of accepting the moving of the first host.

1 more element

A system, comprising:

a relocation host selector module to determine host positions for a Network-on-Chip (NoC) topology, and configured to:
select, from a plurality of hosts of the NoC topology, a first host based on a weight assigned to the first host;
select a location from a plurality of locations that neighbors a second host from the plurality of hosts of the NoC topology, the second host determined from at least one probability assigned to at least one of the plurality of hosts from a first probabilistic acceptance function, based on at least one probability assigned to at least one of the plurality of locations that neighbors the second host from a second probabilistic acceptance function;
and
move the first host from one location another location for a relocation decision that is a result indicative of accepting the moving of the first host;
and
a relocation acceptance function module configured to determine the relocation decision based on a third probabilistic acceptance function.

4 more elements

Dependencies are inferred from the claim text.

Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Life of this patent

Automatically connecting SoCs IP cores to interconnect nodes to minimize global latency and reduce interconnect cost

Life of this patent

Abstract

Claims21