Power envelope analysis for the thermal optimization of multi-chip modules
AssigneeSTATS ChipPAC Pte. Ltd.
InventorsChien Ouyang, Xiao Gu, Yonghyuk Jeong, Michael Mingliang Liu
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Abstract
A semiconductor device is made by calculating a thermal resistance matrix for the semiconductor device. A plurality of maximum junction temperatures for the plurality of die of the semiconductor device is selected. A plurality of power envelope surfaces are calculated for the semiconductor device based on the thermal resistance matrix and the maximum junction temperatures. A plurality of powers is selected for the plurality of die. The plurality of powers are compared against the plurality of power envelope surfaces to determine a plurality of risk values.
Claims25
A method of making a semiconductor device, comprising:
- calculating a thermal resistance matrix for the semiconductor device;
- selecting a plurality of maximum junction temperatures for a plurality of die of the semiconductor device;
- calculating a plurality of power envelope surfaces for the semiconductor device based on the thermal resistance matrix and maximum junction temperatures;
- selecting a plurality of powers for the plurality of die;
- and
- comparing the plurality of powers against the plurality of power envelope surfaces to determine a plurality of risk values.
A method of making a semiconductor device, comprising:
- calculating a thermal resistance matrix for the semiconductor device;
- selecting a plurality of maximum junction temperatures for a plurality of die of the semiconductor device;
- selecting a plurality of powers for the plurality of die;
- calculating a product of the thermal resistance matrix and a matrix of the plurality of powers;
- and
- determining whether the product is less than a matrix of the plurality of maximum junction temperatures, and therefore the plurality of powers is thermally safe for the semiconductor device, or whether the product is greater than or equal to the matrix of the plurality of maximum junction temperatures, and therefore the plurality of powers is thermally risky for the semiconductor device.
A method of making a semiconductor device, comprising:
- calculating a thermal resistance matrix;
- selecting a plurality of powers for a plurality of die for the semiconductor device;
- and
- determining whether the selected plurality of powers is thermally safe by multiplying a matrix of the plurality of powers and the thermal resistance matrix;
- calculating a plurality of power envelope surfaces for the semiconductor device based on the thermal resistance matrix;
- and
- comparing the plurality of powers against the plurality of power envelope surfaces to determine a plurality of risk values.
A method of making a semiconductor device, comprising:
- calculating a thermal resistance matrix;
- selecting a plurality of powers for a plurality of die for the semiconductor device;
- determining whether the selected plurality of powers is thermally safe by multiplying a matrix of the plurality of powers and the thermal resistance matrix;
- selecting a plurality of maximum junction temperatures;
- and
- comparing a product of the matrix of the plurality of powers and the thermal resistance matrix against a matrix of the plurality of maximum junction temperatures.
Dependencies are inferred from the claim text.