US 7,673,273 B2 · MPGA products based on a prototype FPGA

Abstract

A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.

Claims20

Dependent claims

An integrated circuit design platform, comprising:

a field programmable gate array (FPGA) prototype device comprised of:
a circuits layout comprising a plurality of field programmable logic blocks and a plurality of layers of field programmable interconnects;
and
a set of input/output pad structures;
and
a first region within the circuits layout, said region having registers at one or more boundaries of the region, said registers capable of coupling to said input/output pad structures;
and
a metal programmable gate array (MPGA) production device fabricated separately from the FPGA prototype device, the MPGA production device comprised of:
a substantially identical circuit layout as in the first region of the FPGA;
and
a substantially identical layout of one or more layers of programmable interconnects as in the first region of the FPGA;
wherein, a design mapped to the first region of the FPGA is identically mapped to the MPGA.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/712,380Filed 1 Mar 2007 · continuation in part

Priority

8 Jul 2002

Published

US 2007/0103192 A15 Jul 2007

Granted

2 Mar 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 30/347
For reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]: physical level, e.g. placement or routing
H10D 89/601
Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]:…
G06F 30/30
Computer-aided design [CAD]: circuit design
G06F 30/34
Circuit design: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Family

Application60/393,763Us provisional application · filed 8 Jul 2002

Application60/397,070Us provisional application · filed 22 Jul 2002

Application10/267,511Parent of this continuation · filed 8 Oct 2002

Application10/825,194Parent of this continuation · filed 16 Apr 2004

Application11/384,116Parent of this continuation · filed 20 Mar 2006

Application11/645,313Parent of this continuation-in-part · filed 26 Dec 2006

US 2007/0152708 A1Pre-grant publication · published 5 Jul 2007

US 7,356,799 B2Parent of this continuation

Application11/645,313Parent of this continuation

US 6,992,503 B2Parent of this continuation

US 6,747,478 B2Parent of this continuation

US 2004/0004496 A1Published application

US 2004/0196065 A1Published application

US 2006/0158217 A1Published application

US 2007/0103192 A1Published application

US 7,627,848 B2Related patent

US 7,673,273 B2This patent

From the US filing history. Foreign family members aren’t listed.

MPGA products based on a prototype FPGA

Life of this patent

MPGA products based on a prototype FPGA

Life of this patent

Abstract

Claims20