Application-specific integrated circuit (ASIC) synthesis based on lookup table (LUT) mapping and optimization

A system comprising:

• a memory storing instructions;
• and
• a processor device, coupled with the memory and to execute the instructions, the instructions when executed cause the processor device to:
• access a description of a design of a circuit, the description comprising a logic network that implements a functionality of the circuit;
• and
• perform two or more iterations, each iteration comprising:
• selecting a lookup table (LUT) size k;
• mapping a current directed acyclic graph (DAG) representation of the logic network into a network of k-LUTs, wherein a k-LUT is a lookup table that can represent a function of k variables;
• decomposing the network of k-LUTs into a trial DAG representation;
• and
• updating the current DAG representation in accordance with a quality of the trial DAG representation;
• and
• synthesizing a final DAG representation from the iterations to a netlist of standard cells.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processor device, cause the processor device to:

• access a description of an application-specific integrated circuit (ASIC), the description comprising a logic network that implements a functionality of the ASIC;
• and
• perform two or more iterations, each iteration comprising:
• selecting a lookup table (LUT) size k;
• mapping a current representation of the logic network into a network of k-LUTs, wherein a k-LUT is a lookup table that can represent any function of k variables;
• decomposing the improved network of k-LUTs into a trial representation, including improving the network of k-LUTs and/or improving the trial representation;
• and
• updating the current representation in accordance with a quality of the trial representation;
• and
• synthesizing a final representation from the iterations to a netlist of standard cells.