G01R 31/318508
Board level test
Official title: {Board Level Test, e.g. P1500 Standard (features related to boundary scan G01R31/318533)}
G01R31/318508 (Board level test) appears on 97 US grants and 95 published applications in this corpus.
Search patents in G01R- Granted patents
- 97
- Published applications
- 95
- Assignees
- 48
- Inventors
- 124
- Latest grant
- 25 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 1 |
| 2002 | 0 | 2 |
| 2003 | 1 | 3 |
| 2004 | 1 | 6 |
| 2005 | 4 | 2 |
| 2006 | 3 | 1 |
| 2007 | 4 | 3 |
| 2008 | 2 | 3 |
| 2009 | 7 | 3 |
| 2010 | 7 | 1 |
| 2011 | 5 | 4 |
| 2012 | 3 | 7 |
| 2013 | 6 | 8 |
| 2014 | 7 | 4 |
| 2015 | 3 | 4 |
| 2016 | 7 | 5 |
| 2017 | 7 | 7 |
| 2018 | 3 | 4 |
| 2019 | 5 | 4 |
| 2020 | 3 | 3 |
| 2021 | 3 | 3 |
| 2022 | 4 | 6 |
| 2023 | 3 | 3 |
| 2024 | 3 | 4 |
| 2025 | 2 | 4 |
| 2026 | 2 | 0 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Integrated circuit, memory device including the integrated circuit, and method of operating the same25 Aug 2026US 12,716,943 B2Samsung Electronics Co., Ltd.
- Apparatus and method for testing semiconductor devices17 Feb 2026US 12,553,945 B2Testmetrix, Inc.
- 3D stacked die test architecture4 Nov 2025US 12,461,148 B2Texas Instruments Incorporated
- JTAG standard pin test system30 Sep 2025US 12,429,521 B2Inventec Corporation
- Test system, test method, and non-transitory computer readable medium19 Nov 2024US 12,146,910 B2Kioxia Corporation
- Stacked parametric measurement unit test circuit2 Oct 2025US 2025/0306107 A1Elevate Semiconductor, Inc.
- Jtag standard pin test system12 Jun 2025US 2025/0189581 A1Inventec Corporation
- Predictive and adaptive infield testing based on silicon health information29 May 2025US 2025/0172611 A1Intel Corporation
- Boundary scan for shared analog and digital pins13 Feb 2025US 2025/0052813 A1Texas Instruments Incorporated
- Apparatus and Method for Testing Semiconductor Devices3 Oct 2024US 2024/0329134 A1Testmetrix, Inc.
Most cited
By later US patents
- Input-output device testing including embedded tests42US 7,653,849 B1Virage Logic Corporation · 2010
- Method and apparatus for testing embedded cores39US 7,313,739 B2Analog Devices, Inc. · 2007
- Method for testing electronic assemblies28US 4,556,840 AHoneywell Information Systems Inc. · 1985
- Scan interface chip (SIC) system and method for scan testing electronic systems24US 6,760,876 B1Silicon Graphics, Inc. · 2004
- Integrated circuit chip with communication means enabling remote control of testing means of IP cores of the integrated circuit23US 7,725,784 B2Institut National Polytechnique de Grenoble · 2010