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US 6,760,876 B1Granted
Scan interface chip (SIC) system and method for scan testing electronic systems
AssigneeSilicon Graphics, Inc.
InventorLouis C. Grannis, III
Life of this patent
Estimating the term…
Abstract
A scan test interface system and method provides an interface between upstream scan test devices and downstream scan test devices. The scan test interface system and method receives scan test signals, facilitates flexible configuration of scan test signals and transmits scan test signals on subordinate scan test chains. A scan test interface includes a scan test interface register, a system interface, a scan test interface controller, a board interface and a selection circuit.
Claims38
A scan test interface comprising:
- a scan test interface register for storing information related to scan test operations;
- a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;
- a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;
- a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain;
- and
- a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain, wherein said scan test interface supports scan test operations on multiple separate downstream scan test chains and concatenates scan test information from said separate down stream scan test chains.
3 more elements
A scan test interface comprising:
- a scan test interface register for storing information related to scan test operations;
- a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;
- a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;
- a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain;
- and
- a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports for communicating a separate set of scan test signals for each downstream scan test chain;
- a scan interface chip (SIC), wherein said board interface of said SIC further comprises a set of scan test chain communication ports that communicate separate standard JTAG signals from other scan test chains said SIC services, wherein said scan test chain communication ports behave as pseudo open-collector outputs.
4 more elements
A scan test system comprising:
- a plurality of scan interface chips (SIC)s including a first SIC and a second SIC;
- a first plurality of downstream scannable devices arranged in separate scan test chains operatively coupled to the first SIC, the first plurality of downstream scannable devices operating in a first voltage and clock domain;
- a second plurality of downstream scannable devices arranged in separate scan test chains operatively coupled to the second SIC, the second plurality of downstream scannable devices operating in a second voltage and clock domain different from the first voltage and clock domain;
- wherein each one of the plurality of SICs communicates a separate set of scan test signals to at least one of said scan test chains;
- and
- a scan test system controller coupled to each of the plurality of SICs, said scan test system controller communicating said scan test signals to and from said plurality of SICs.
3 more elements
A scan test interface method comprising the steps of:
- receiving scan test information from upstream scan test devices;
- transmitting scan test information to a plurality of discrete downstream devices;
- receiving scan test information from the plurality of discrete downstream devices;
- transmitting scan test information to upstream scan test devices;
- facilitating flexible scan test operations;
- and
- supporting scan testing of multiple subordinate separate scan test chains with a separate set of scan test signals to each downstream scan test chain.
4 more elements
A scan test interface method comprising:
- receiving scan test information from upstream scan test devices;
- transmitting scan test information to downstream devices;
- receiving scan test information from downstream devices;
- transmitting scan test information to upstream scan test devices;
- facilitating flexible scan test operations;
- receiving a scan test interface address;
- retrieving an address identifying said scan test interface;
- comparing the received address to the retrieved address;
- and
- enabling a scan test interface to participate in a scan test operation if the retrieved address and the received address are the same.
7 more elements
A scan test interface method comprising:
- receiving scan test information from upstream scan test devices;
- transmitting scan test information to downstream devices;
- receiving scan test information from downstream devices;
- transmitting scan test information to upstream scan test devices;
- facilitating flexible scan test operations;
- and
- facilitating voltage conversion of downstream scan test signals, wherein said facilitating voltage conversion includes the step of utilizing a pseudo OC output method to match a scan test chain operation voltage.
4 more elements
A scan test interface comprising:
- a scan test interface register for storing information related to scan test operations;
- a system interface coupled to said scan test interface register, said system interface provides a communication port for communicating scan test operation information between said scan test interface and upstream scan test devices;
- a scan test interface controller coupled to said scan test interface register, said scan test interface controller directs operations of said scan test interface register;
- a selection circuit coupled to said scan test interface register, said selection circuit facilitates selection of a scan test chain and tracks a primary TAP state of a scan test chain;
- a board interface coupled to said selection circuit, said board interface includes multiple scan test chain ports that provide communication ports for communicating a separate set of scan test signals for each downstream scan test chain;
- and
- a number in can (NIC) circuit for retrieval of information from a plurality of downstream devices.
4 more elements
A scan test interface method comprising:
- receiving scan test information from upstream scan test devices;
- transmitting scan test information to discrete downstream devices;
- tracking a primary TAP controller state associated with a downstream scan test chain and storing the state of a primary TAP controller and the scan test information transmitted to discrete downstream devices;
- receiving scan test information from discrete downstream devices;
- transmitting scan test information to upstream scan test devices;
- and
- facilitating flexible scan test operations.
4 more elements
A scan test interface method comprising the steps of:
- receiving scan test information from upstream scan test devices;
- transmitting scan test information to downstream devices;
- tracking a primary TAP controller state associated with a downstream scan test chain;
- receiving scan test information from downstream devices;
- transmitting scan test information to upstream scan test devices;
- facilitating flexible scan test operations;
- tracking the state of scan test signals transmitted from a scan test interface to a subordinate scan test chain;
- encoding the state of the scan test signal transmitted from a scan test interface to a subordinate scan test chain;
- and
- storing the state of a scan test signal transmitted from a scan test interface to a subordinate scan test chain.
7 more elements
Dependencies are inferred from the claim text.