Integrated circuit, memory device including the integrated circuit, and method of operating the same

A memory device comprising an integrated circuit, the integrated circuit comprising:

• a first block including a first wrapper and a first area of circuit elements isolated by the first wrapper;
• a target block external to the first block, the target block including a second wrapper and a third wrapper;
• and
• a second block external to the target block, the second block including a fourth wrapper and a fourth area of circuit elements isolated by the fourth wrapper;
• wherein the target block includes a second area of circuit elements isolated by the second wrapper, and a third area of circuit elements isolated by the third wrapper;
• wherein the second wrapper is connected to the first wrapper and configured to perform a test operation on the second area;
• wherein the third wrapper is connected to the fourth wrapper and configured to perform a test operation on the third area;
• wherein the first block is configured to receive a test signal, and the first wrapper included in the first block is configured to input the test signal to the second area of circuit elements included in the target block;
• wherein the second wrapper is configured to receive the test signal after the test signal has been input to the second area of circuit elements by the first wrapper and has passed through the second area of circuit elements, without the second wrapper having input the test signal to the second area of circuit elements;
• wherein the first area is an edge area of the first block positioned between the first wrapper and the second wrapper;
• wherein the second area is an edge area of the target block positioned between the first wrapper and the second wrapper;
• wherein the third area is another edge area of the target block positioned between the third wrapper and the fourth wrapper;
• and
• wherein the fourth area is an edge area of the second block positioned between the third wrapper and the fourth wrapper.

A method of operating an integrated circuit to perform a test on a memory device, the method comprising:

• inputting a test signal to a first wrapper of a first block;
• forming a wrapper chain by using the first wrapper, a second wrapper of a target block, a third wrapper of the target block, and a fourth wrapper of a second block;
• inputting, via the first wrapper of the first block, the test signal to an area of circuit elements included in the target block;
• receiving, via the second wrapper of the target block, the test signal after the test signal has been input to the area of circuit elements by the first wrapper and has passed through the area of circuit elements, without the second wrapper having input the test signal to the area of circuit elements;
• and
• extracting, from the wrapper chain, an output value generated in response to the test signal;
• wherein the area of circuit elements is an edge area of the target block adjacent to the second wrapper and positioned between the first wrapper and the second wrapper.