Input-output device testing including embedded tests
AssigneeVirage Logic Corporation
InventorSassan Tabatabaei
Life of this patent
Estimating the term…
Abstract
Integrated circuits may include at least an instruction processor and input-output subsystems. Each input-output subsystem includes a wrapper circuit a wrapper circuit controlled by the instruction processor. The wrapper circuit includes two or more scan registers, where a data value stored in each scan register can be shifted out for analysis. The wrapper circuit also includes two or more update registers to transfer stored data values between itself and an associated scan register. The wrapper circuit also includes a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os couple to an external tester.
Claims21
An apparatus, comprising:
- an integrated circuit containing
- an instruction test processor;
- and
- a plurality of input-output circuits (I/O) mutually coupled in a chain and each including
- an output driver circuit coupled to an input-output port,
- an input receiver circuit coupled to the input-output port,
- a wrapper circuit controlled by the instruction processor and including
- two or more scan registers, where a data value is stored in each scan register,
- two or more update registers to transfer stored data values between itself and an associated scan register, and
- a set of combinatorial logic coupled to the scan registers, the update registers and the instruction test processor, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os directly couple to an external tester.
A method, comprising:
- performing one or more embedded tests on a plurality of input-output circuits (I/O) mutually coupled in a chain, wherein at least two I/Os of the plurality of I/Os but less than all of the plurality of I/Os directly couple to an external tester;
- and
- sending signals to a wrapper circuit associated with a first I/O from the plurality of I/Os from an on-chip processor during the one or more embedded tests to control an operational mode of one or more registers in the wrapper circuit.
Dependencies are inferred from the claim text.