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US 12,461,148 B2Granted
3D stacked die test architecture
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
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Abstract
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
Claims20
A device comprising:
- a parallel test data input (PTDI) bus having a first PTDI line and a second PTDI line;
- a parallel test data input/output (PTDIO) bus having a first PTDIO line and a second PTDIO line;
- a first surface coupled to the PTDI bus and the PTDIO bus;
- a second surface opposite the first surface, wherein the second surface is coupled to the PTDI bus and the PTDIO bus;
- a parallel test circuit coupled to the first PTDI line and the second PTDI line, wherein the parallel test circuit includes a first parallel test data output (PTDO) and a second PTDO;
- and
- a test circuit coupled to the first PTDO, the second PTDO, the first PTDIO line, and the second PTDIO line.
4 more elements
A system comprising:
- a first die including:
- a first parallel test data input (PTDI) bus;
- a first parallel test data input/output (PTDIO) bus;
- a first parallel test circuit coupled to the first PTDI bus, wherein the first parallel test circuit includes a first set of parallel test data outputs (PTDOs);
- and
- a first test circuit coupled to the first set of PTDOs and the first PTDIO bus;
- and
- a second die coupled to the first die, wherein the second die includes:
- a second PTDI bus coupled to the first PTDI bus;
- a second PTDIO bus coupled to the second PTDI bus;
- a second parallel test circuit coupled to the second PTDI bus, wherein the second parallel test circuit includes a second set of PTDOs;
- and
- a second test circuit coupled to the second set of PTDOs and the second PTDIO bus.
10 more elements
A device comprising:
- a parallel test data input/output (PTDIO) bus having a first PTDIO line, a second PTDIO line, and a third PTDIO line;
- a first surface coupled to the PTDIO bus;
- a second surface opposite the first surface, wherein the second surface is coupled to the PTDIO bus;
- a parallel test circuit including a first parallel test data output (PTDO) and a second PTDO;
- a first comparator coupled to the first PTDO and the first PTDIO line, wherein the first comparator includes a first comparator output;
- a second comparator coupled to the second PTDO and the second PTDIO line, wherein the second comparator includes a second comparator output;
- and
- a gate circuit coupled to the first comparator output and the second comparator output,
- wherein the gate circuit includes an output coupled to the third PTDIO line.
6 more elements
Dependencies are inferred from the claim text.