Jtag standard pin test system

A JTAG standard pin test system, comprising:

• a to-be-tested board, having to-be-tested slots, wherein the to-be-tested slots are electrically connected to form different to-be-tested series chains;
• riser cards, wherein each of the riser cards has a riser card insertion interface, a riser-card edge-connector interface, a first JTAG (joint test action group) input interface, a first JTAG output interface, a second JTAG input interface, and a second JTAG output interface, wherein test data input (TDI) pins of the riser card insertion interface, the riser-card edge-connector interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, test data output (TDO) pins of the riser card insertion interface, the riser-card edge-connector interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, test clock (TCK) pins of the riser card insertion interface, the riser-card edge-connector interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, test mode select (TMS) pins of the riser card insertion interface, the riser-card edge-connector interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other, and test reset (TRST) pins of the riser card insertion interface, the riser-card edge-connector interface, the first JTAG input interface, the first JTAG output interface, the second JTAG input interface, and the second JTAG output interface are electrically connected to each other,
• wherein the riser-card edge-connector interface of each of the riser cards is inserted into a corresponding one of the to-be-tested slots, so that the inserted riser-card edge-connector interface is electrically connected to TDI pins, the TDO pins, the TCK pins, the TMS pins, and the TRST pins of the corresponding one of the to-be-tested slots;
• test cards, wherein each of the test cards has a boundary scan component, a JTAG input interface, a JTAG output interface, and an edge connector interface, wherein TDI pins of the boundary scan component, the JTAG input interface, the JTAG output interface, and the edge connector interface are electrically connected to each other, TDO pins of the boundary scan component, the JTAG input interface, the JTAG output interface, and the edge connector interface are electrically connected to each other, TCK pins of the boundary scan component, the JTAG input interface, the JTAG output interface, and the edge connector interface are electrically connected to each other, TMS pins of the boundary scan component, the JTAG input interface, the JTAG output interface, and the edge connector interface are electrically connected to each other, and TRST pins of the boundary scan component, the JTAG input interface, the JTAG output interface, and the edge connector interface are electrically connected to each other,
• wherein, the edge connector interface of each of the test cards is inserted into the riser card insertion interface of a corresponding one of the riser cards, so that the inserted edge connector interface is electrically connected to the TDI pins, the TDO pins, the TCK pins, the TMS pins, and the TRST pins of the riser card insertion interface of the corresponding one of the riser cards,
• wherein each of the test cards performs a JTAG standard pin test on a JTAG format test signal provided from the corresponding one of the to-be-tested slots and outputs a JTAG format test result signal;
• a test access port (TAP) controller, electrically connected to different to-be-tested series chains, and configured to convert test data into corresponding JTAG format test signals and provide the JTAG format test signals to the different to-be-tested series chains, respectively, receives the JTAG format test result signals from the to-be-tested series chains, and converts the received JTAG format test result signals into response data;
• and
• a test data generating device, electrically connected to the TAP controller, and configured to provide the test data to the TAP controller, and receive the response data corresponding to the to-be-tested slots from the TAP controller.