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US 7,313,739 B2Granted
Method and apparatus for testing embedded cores
AssigneeAnalog Devices, Inc.
InventorsSankaran M. Menon, Luis A. Basto, Tien Dinh, Thomas Tomazin, Juan G. Revilla
Life of this patent
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Abstract
Testing memory devices. An apparatus may include a test module operative to perform a test on a plurality of pipelined memory elements and a fail trace module operative to interrupt the test in response to identifying a failure of a memory element and to store an address of said memory element in a storage unit.
Claims20
Apparatus comprising:
- a pipelined memory including multiple stages and a plurality of memory elements having addresses;
- a test module operative to perform a test on the plurality of memory elements by writing test data to the plurality of memory elements in the pipelined memory, redundantly writing said test data n−1times to the plurality of memory elements, and reading the test data from the plurality of memory elements;
- a first storage unit;
- a comparator to compare test output data that is output from the pipelined memory with data expected to be output from the pipelined memory to identify a failure of a memory element;
- logic to account for a timing latency that arises due to the multiple stages and identify an address of said memory element based on memory addresses of the test data input into the pipelined memory in response to receipt of a notification of the failure from the comparator;
- and
- a fail trace module operative to interrupt the test in response to the identification of the failure of a memory element and to store the identified address of said memory element in the storage unit thereby making the identified address available for output,
- where n is the number of pipeline stages.
5 more elements
A method comprising:
- writing a test pattern to a plurality of memory elements having addresses in a pipelined memory having multiple stages;
- reading the plurality of memory elements in a sequence, wherein said reading comprises reading the test data from the plurality of memory elements and redundantly reading the test data n−1 times from the plurality of memory elements;
- identifying a fault at one of said memory elements;
- accounting for a timing latency that arises due to the multiple stages and identifying an address of said one of said memory elements based on memory addresses of the test pattern and the identifying of the fault;
- storing the identified address of said one of said memory elements thereby making the identified address available for output;
- and
- resuming reading the plurality of memory elements at a next memory element in the sequence,
- where n is the number of pipeline stages.
5 more elements
A method of testing a pipelined memory, comprising:
- writing test data to a plurality of memory elements in the pipeliried memory;
- redundantly writing said test data n−1 times to the plurality of memory elements;
- reading the test data from the plurality of memory elements;
- identifying an address of a failing memory element based on at least some of the read test data;
- and
- making the address of a failing memory element available for output,
- where n is the number of pipeline stages.
4 more elements
A method of testing a pipelined memory, comprising:
- writing test data to a plurality of memory elements in the pipelined memory;
- reading the test data from the plurality of memory elements;
- and
- redundantly reading the test data n−1 times from the plurality of memory elements;
- identifying an address of a failing memory element based on at least some of the read test data;
- and
- making the address of a failing memory element available for output,
- where n is the number of pipeline stages.
5 more elements
Dependencies are inferred from the claim text.