G01R 31/31723
Hardware for routing the test signal within the device under test to
Official title: {Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926)}
G01R31/31723 (Hardware for routing the test signal within the device under test to) appears on 787 US grants and 810 published applications in this corpus.
Search patents in G01R- Granted patents
- 787
- Published applications
- 810
- Assignees
- 174
- Inventors
- 753
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 2 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 9 |
| 2002 | 3 | 3 |
| 2003 | 6 | 13 |
| 2004 | 15 | 28 |
| 2005 | 21 | 36 |
| 2006 | 20 | 29 |
| 2007 | 30 | 34 |
| 2008 | 33 | 31 |
| 2009 | 24 | 26 |
| 2010 | 32 | 32 |
| 2011 | 47 | 32 |
| 2012 | 26 | 31 |
| 2013 | 33 | 37 |
| 2014 | 35 | 33 |
| 2015 | 42 | 43 |
| 2016 | 51 | 60 |
| 2017 | 46 | 80 |
| 2018 | 72 | 61 |
| 2019 | 53 | 37 |
| 2020 | 35 | 30 |
| 2021 | 40 | 30 |
| 2022 | 31 | 27 |
| 2023 | 34 | 30 |
| 2024 | 23 | 16 |
| 2025 | 15 | 11 |
| 2026 | 13 | 11 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- I3C error states test strategy6 Oct 2026US 12,754,235 B2Microchip Technology Incorporated
- Benchmark circuit on a semiconductor wafer and method for operating the same25 Aug 2026US 12,716,941 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Addressable test access port4 Aug 2026US 12,699,134 B2Texas Instruments Incorporated
- Path margin monitoring28 Jul 2026US 12,694,179 B1Synopsys, Inc.
- Techniques for reduction of degradation in channels caused by bias temperature instability5 May 2026US 12,620,981 B2Altera Corporation
- Techniques For Reduction Of Degradation In Channels Caused By Bias Temperature Instability20 Aug 2026US 2026/0246456 A1Altera Corporation
- Test time optimization for identical subsystems in soc13 Aug 2026US 2026/0235673 A1STMicroelectronics International N. V.
- Scan-path integrated circuit memory with output bus feedback9 Jul 2026US 2026/0196286 A1SambaNova Systems, Inc.
- Array of Contact Points on a Die2 Jul 2026US 2026/0186051 A1
- Scan chain segmentation for an integrated circuit21 May 2026US 2026/0140177 A1QUALCOMM Incorporated
Most cited
By later US patents
- Special contact points for accessing internal circuitry of an integrated circuit134US 6,456,099 B1FormFactor, Inc. · 2002
- Device for probe card power bus noise reduction96US 7,005,879 B1International Business Machines Corporation · 2006
- Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer92US 4,884,122 AGeneral Electric Company · 1989
- Tester channel to multiple IC terminals83US 6,798,225 B2FormFactor, Inc. · 2004
- Special contact points for accessing internal circuitry of an integrated circuit81US 6,621,260 B2FormFactor, Inc. · 2003