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US 12,699,134 B2Granted
Addressable test access port
AssigneeTexas Instruments Incorporated
InventorLee D. Whetsel
Life of this patent
Estimating the term…
Abstract
The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.
Claims20
A device comprising:
- a test clock (TCK) terminal;
- a test mode select (TMS) terminal;
- a test data in (TDI) terminal;
- a test access port (TAP) circuit coupled to the TCK terminal, the TMS terminal, and the TDI terminal;
- and
- a second circuit separate from the TAP circuit,
- wherein the second circuit is coupled to the TCK terminal and the TMS terminal,
- wherein the second circuit is configured to respond to a message received by the second circuit from the TMS terminal, and
- wherein the message includes a header, a body, and a trailer.
6 more elements
A device comprising:
- a test clock (TCK) terminal;
- a test mode select (TMS) terminal;
- a test data in (TDI) terminal;
- a test access port (TAP) circuit coupled to the TCK terminal, the TMS terminal, and the TDI terminal;
- and
- a second circuit coupled to the TCK terminal, the TMS terminal, and the TDI terminal, wherein the second circuit is separate from the TAP circuit;
- and
- a TAP access mode detector circuit coupled to the TMS terminal,
- wherein the TAP access mode detector circuit is configured to deliver a mode signal to the TAP circuit and the second circuit in response to the TMS terminal,
- wherein in response to a first logic level of the mode signal, the second circuit is enabled and the TAP access mode detector circuit is disabled, and
- wherein in response to a second logic level of the mode signal, the second circuit is disabled and the TAP access mode detector circuit is enabled.
8 more elements
A device comprising:
- a test clock (TCK) terminal;
- a test mode select (TMS) terminal;
- a test data in (TDI) terminal;
- a test access port (TAP) circuit coupled to the TCK terminal, the TMS terminal, and the TDI terminal;
- and
- a second circuit separate from the TAP circuit,
- wherein the second circuit is coupled to the TCK terminal and the TMS terminal,
- wherein the second circuit is configured to operate independent of the TAP circuit in response to inputs received from the TCK terminal and the TMS terminal,
- wherein the second circuit is configured to respond to a message received by the second circuit from the TMS terminal,
- wherein the message includes a header, a body, and a trailer, and
- wherein the second circuit is configured to initiate or terminate an address input operation in response to the trailer of the message.
8 more elements
Dependencies are inferred from the claim text.