Test time optimization for identical subsystems in soc
AssigneeSTMicroelectronics International N.V.
InventorHarish Kumar
Life of this patent
Estimating the term…
Abstract
According to an embodiment, a test architecture for system-on-chip (SoC) enables testing of replicated blocks while maintaining comprehensive fault detection. The architecture includes parallel test pattern application to multiple identical blocks through modified scan logic, with responses compared through both AND-gate and XOR-gate based networks. The AND-gate network provides quick pass/fail indication, while the XOR-gate network prevents fault masking by detecting mismatches between corresponding outputs. A multiplexer enables individual block observation during debug operations.
Claims20
A system-on-chip (SoC), comprising:
- a plurality of identical replicated blocks, each block having a plurality of scan outputs;
- a first comparison network comprising:
- a plurality of AND gates, each AND gate having inputs coupled to corresponding scan outputs from the replicated blocks,
- a first multiplexer having inputs coupled to outputs of the AND gates and to individual scan outputs from the replicated blocks, and
- a first flip-flop having an input coupled to an output of the first multiplexer;
- and
- a second comparison network comprising:
- a plurality of XOR gates, each XOR gate having inputs coupled to corresponding scan outputs from pairs of the replicated blocks,
- an OR gate having inputs coupled to outputs of the XOR gates, and
- a second flip-flop having an input coupled to an output of the OR gate.
A method of testing replicated blocks in a system-on-chip (SoC), the method comprising:
- generating test patterns for a first replicated block;
- simultaneously applying the test patterns to a plurality of identical replicated blocks through modified scan logic;
- performing first comparisons of corresponding scan outputs through AND gates;
- performing second comparisons of corresponding scan outputs through XOR gates;
- combining outputs of the XOR gates through an OR gate;
- capturing results of the first comparisons in a first flip-flop;
- capturing results of the second comparisons in a second flip-flop;
- and
- evaluating test results based on outputs of both flip-flops.
A design for test (DFT) architecture for testing a system-on-chip (SoC) with a plurality of scan chains distributed across identical replicated blocks, the DFT architecture comprising:
- a first comparison network providing parallel test capability through AND gates coupled to corresponding scan outputs from the replicated blocks;
- a second comparison network preventing fault masking through XOR gates coupled to corresponding scan outputs from pairs of the replicated blocks;
- selection logic enabling individual observation of replicated block outputs during debug operations;
- and
- capture logic registering results from both comparison networks.
Dependencies are inferred from the claim text.