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AssigneeGeneral Electric Company
InventorsCharles W. Eichelberger, Robert J. Wojnarowski, Kenneth B. Welles, II
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The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
An integrated circuit chip package including chips of an electronic system therein, comprising:
The package of claim I in which a second polymer film is disposed over said first film and a second metallization pattern is disposed over said second film, said second metallization pattern including connections to the first recited metallization pattern.
The package of claim I wherein:
Dependencies are inferred from the claim text.