G01R 31/31717
Interconnect testing
Official title: {Interconnect testing (by scan techniques see G01R31/31855)}
G01R31/31717 (Interconnect testing) appears on 189 US grants and 203 published applications in this corpus.
Search patents in G01R- Granted patents
- 189
- Published applications
- 203
- Assignees
- 109
- Inventors
- 406
- Latest grant
- 9 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 1 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 1 | 1 |
| 2003 | 1 | 6 |
| 2004 | 3 | 4 |
| 2005 | 3 | 11 |
| 2006 | 15 | 14 |
| 2007 | 12 | 20 |
| 2008 | 8 | 11 |
| 2009 | 16 | 18 |
| 2010 | 18 | 12 |
| 2011 | 15 | 10 |
| 2012 | 6 | 6 |
| 2013 | 6 | 12 |
| 2014 | 13 | 8 |
| 2015 | 9 | 2 |
| 2016 | 6 | 7 |
| 2017 | 8 | 4 |
| 2018 | 3 | 5 |
| 2019 | 5 | 8 |
| 2020 | 10 | 4 |
| 2021 | 3 | 8 |
| 2022 | 8 | 2 |
| 2023 | 4 | 4 |
| 2024 | 4 | 12 |
| 2025 | 6 | 8 |
| 2026 | 2 | 6 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Test and repair of interconnects between chips9 Jun 2026US 12,650,459 B2Intel Corporation
- Die-to-die connectivity monitoring2 Jun 2026US 12,644,924 B2Proteantecs Ltd.
- Integrated circuit testing method and system30 Dec 2025US 12,510,593 B2TouchNetix Limited
- Enhanced direct current (DC) built-in-self-test (BIST) coverage for optical engines and advanced packaging2 Dec 2025US 12,487,275 B2Cisco Technology, Inc.
- Circuitry for electrical redundancy in bonded structures30 Sep 2025US 12,431,449 B2Adeia Semiconductor Bonding Technologies Inc.
- Multi-phase synchronized method for lane margining1 Oct 2026US 2026/0299021 A1SK hynix Inc.
- Stacked semiconductor apparatus, method of detecting fault, and method of repairing fault2 Apr 2026US 2026/0096480 A1Electronics and Telecommunications Research Institute
- Apparatus, system, and method of system on chip (soc) functional safety (fusa)19 Mar 2026US 2026/0079203 A1Mobileye Vision Technologies Ltd.
- Chiplet, chip, and chip debugging method5 Mar 2026US 2026/0063711 A1Sanechips Technology Co., Ltd.
- Circuit and method for interconnect test12 Feb 2026US 2026/0043848 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Memory circuit for use in hardware emulation system197US 6,732,068 B2Quickturn Design Systems, Inc. · 2004
- Method and apparatus for evaluating and optimizing a signaling system146US 7,490,275 B2Rambus Inc. · 2009
- Emulation system with time-multiplexed interconnect117US 5,960,191 AQuickturn Design Systems, Inc. · 1999
- Method and apparatus for dynamically testing electrical interconnect101US 6,694,464 B1Quickturn Design Systems, Inc. · 2004
- Emulation system with time-multiplexed interconnect90US 6,377,912 B1Quickturn Design Systems, Inc. · 2002