Test and repair of interconnects between chips

An apparatus, comprising:

• a set of receive lanes on a first chip;
• a set of interconnects on the first chip, wherein each receive lane of the set of receive lanes is connected to a respective interconnect of the set of interconnects, and the set of interconnects of the first chip are to connect to a second chip;
• a signal generator on the first chip;
• for each receive lane of the set of receive lanes, a respective switch on the first chip;
• a comparator on the first chip, wherein in a test of each receive lane of the set of receive lanes which does not involve the second chip, the respective switches are turned off, and to test each receive lane of the set of receive lanes, one receive lane at a time, the signal generator is to apply a first periodic signal to the receive lane under test and concurrently apply a second periodic signal to other receive lanes of the set of receive lanes, and the comparator is to determine whether a time-shifted version of the first periodic signal is detected on the receive lane under test, wherein in a test of each receive lane of the set of receive lanes which involves the second chip, the respective switches are turned on, and to test each receive lane of the set of receive lanes, one receive lane at a time, the comparator is to determine whether a time-shifted version of a third periodic signal is received on the receive lane under test from the second chip via one of the respective interconnects;
• and
• an error analyzer coupled to the comparator, the error analyzer is to provide a repair signature which identifies one or more replacement lanes for one or more defective lanes in response to the test of each lane of the set of lanes which does not involve the second chip and in response to the test of each lane of the set of lanes which does involve the second chip.

An apparatus, comprising:

• a set of transmit lanes on a first chip;
• a set of interconnects on the first chip, wherein each lane of the set of transmit lanes is connected to a respective interconnect of the set of interconnects on the first chip;
• a set of receive lanes on a second chip;
• a set of interconnects on the second chip, wherein each lane of the set of receive lanes is connected to a respective interconnect of the set of interconnects on the second chip;
• a signal generator on the first chip;
• and
• a comparator on the second chip;
• wherein the signal generator, to test each transmit lane of the set of transmit lanes, is to apply a first periodic signal to the transmit lane under test and to apply a second period signal to other lanes of the set of transmit lanes, while the comparator is to determine whether a time-shifted version of the first periodic signal is received on a corresponding receive lane of the set of receive lanes.