Circuit and method for interconnect test
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMohammed Moiz Khan, Sandeep K. Goel, Yun-Han Lee
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMohammed Moiz Khan, Sandeep K. Goel, Yun-Han Lee
Estimating the term…
A circuit includes a first die including first and second interface circuits, a second die including third and fourth interface circuits, and a first interconnect configured to operatively couple the first die through the first and second interface circuits to the second die through the third and fourth interface circuits. During a first operation stage, the first interface circuit to the fourth interface circuit are each configured to receive control data based on a first frequency, the control data including a series of scan data bits for testing the first interconnect. During a second operation stage following the first operation stage, the first interface circuit to the fourth interface circuit are each configured to receive test data based on a second frequency, the test data including a series of capture data bits for testing the first interconnect. The second frequency is substantially higher than the first frequency.
A circuit, comprising:
A circuit, comprising:
A method, comprising:
Dependencies are inferred from the claim text.