US 6,694,464 B1Granted

Method and apparatus for dynamically testing electrical interconnect

AssigneeQuickturn Design Systems, Inc.

InventorsBarton L. Quayle, Stephen P. Sample

Life of this patent

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Abstract

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common input/output pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system. A method for dynamically testing the interconnect between integrated circuits is also disclosed.

Claims24

Dependent claims

A method for dynamically testing interconnections between a first integrated circuit and a second integrated circuit, the first and second integrated circuits having interconnect placing pins on them in electrical communication, the method comprising:

programming a first cell into the first integrated circuit such that said first cell is in electrical communication with a first pin on the first integrated circuit, said first cell comprising a first storage element;
programming a second cell into the second integrated circuit such that said second cell is in electrical communication with a first pin on the second integrated circuit, said second cell comprising a second storage element;
programming a predetermined data value into said first cell;
programming a predetermined expected data value into said second cell;
transmitting said predetermined data value from said first integrated circuit from said first cell, through said first pin on the first integrated circuit, the interconnect, said first pin on the second integrated circuit, to said second cell programmed into said second integrated circuit;
on said second integrated circuit, comparing said predetermined expected value to said predetermined data value received by said second integrated circuit;
and
outputting an error flag from said second integrated circuit if said predetermined data value received by said second integrated circuit and said predetermined expected value do not match.

5 more elements

An apparatus for testing electrical integrity of interconnect between a first integrated circuit and a second integrated circuit, said first integrated circuit comprising a first pin, said second integrated circuit comprising a second pin, said first pin and said second pin in electrical communication with each other through an interconnect, the apparatus comprising:

a first cell in electrical communication with said first pin on said first integrated circuit, said first cell comprising a first pattern match circuit, said first cell storing a predetermined data value;
a second cell in electrical communication with said second pin on said second integrated circuit, said second cell comprising a second pattern match circuit, said s econd cell storing a predetermined expected value;
and
said second pattern match circuit comparing said predetermined data value transmitted from said first integrated circuit with said predetermined expected value stored in said second cell;
said second pattern match circuit outputting an error signal if said predetermined data value received by said first integrated circuit does not match said predetermined expected value.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/695,103Filed 23 Oct 2000 · continuation in part
Priority: 30 May 1997
Granted: 17 Feb 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G01R 31/31717
Input or output aspects: interconnect testing
G01R 31/2853
Testing of integrated circuits [IC]: electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
G06F 30/331
Using simulation: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
G01R
Measuring electric variables

Family

Application08/865,741Parent of this continuation · filed 30 May 1997
Application09/374,444Parent of this continuation-in-part · filed 13 Aug 1999
US 6,377,912 B1Parent of this continuation-in-part
Application09/374,444Parent of this continuation
US 5,960,191 AParent of this continuation
US 6,694,464 B1This patent

From the US filing history. Foreign family members aren’t listed.