Apparatus, system, and method of system on chip (soc) functional safety (fusa)

An apparatus comprising:

• a System on Chip (SoC) comprising:
• a plurality of Integrated Circuits (ICs);
• at least one Network on Chip (NoC) to communicate information between the plurality of ICs;
• a plurality of parity circuits on a plurality of IC-NoC paths between the plurality of ICs and the at least one NoC, the plurality of parity circuits configured according to a same parity protocol, wherein a parity circuit on an IC-NoC path between an IC and the at least one NoC comprises a parity generator and a parity checker, the parity generator configured to generate a first parity value for first information provided from the IC to the at least one NoC, the parity checker configured to selectively provide a parity-error signal based on a parity check of a second parity value of second information provided from the at least one NoC to the IC;
• and
• a Functional Safety (FuSA) manager configured to generate FuSA information based on one or more parity-error signals from the plurality of parity circuits.