H10W 90/737
Between a chip and a laterally-adjacent lead frame, conducting package substrate or
Official title: {between a chip and a laterally-adjacent lead frame, conducting package substrate or heat sink}
H10W90/737 (Between a chip and a laterally-adjacent lead frame, conducting package substrate or) appears on 284 US grants and 199 published applications in this corpus.
Search patents in H10W- Granted patents
- 284
- Published applications
- 199
- Assignees
- 133
- Inventors
- 557
- Latest grant
- 18 Aug 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 2 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 3 | 0 |
| 1988 | 1 | 0 |
| 1989 | 10 | 0 |
| 1990 | 5 | 0 |
| 1991 | 8 | 0 |
| 1992 | 6 | 0 |
| 1993 | 6 | 0 |
| 1994 | 10 | 0 |
| 1995 | 7 | 0 |
| 1996 | 4 | 0 |
| 1997 | 10 | 0 |
| 1998 | 6 | 0 |
| 1999 | 6 | 0 |
| 2000 | 8 | 0 |
| 2001 | 7 | 2 |
| 2002 | 10 | 8 |
| 2003 | 7 | 15 |
| 2004 | 9 | 17 |
| 2005 | 16 | 17 |
| 2006 | 15 | 13 |
| 2007 | 8 | 13 |
| 2008 | 11 | 11 |
| 2009 | 7 | 11 |
| 2010 | 15 | 33 |
| 2011 | 21 | 25 |
| 2012 | 27 | 3 |
| 2013 | 7 | 1 |
| 2014 | 5 | 4 |
| 2015 | 4 | 2 |
| 2016 | 3 | 2 |
| 2017 | 2 | 0 |
| 2018 | 0 | 0 |
| 2019 | 1 | 2 |
| 2020 | 0 | 3 |
| 2021 | 4 | 4 |
| 2022 | 1 | 4 |
| 2023 | 3 | 0 |
| 2024 | 1 | 4 |
| 2025 | 0 | 2 |
| 2026 | 2 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Power semiconductor module18 Aug 2026US 12,713,991 B2Infineon Technologies AG
- Method to connect power terminal to substrate within semiconductor package3 Feb 2026US 12,543,611 B2Littelfuse, Inc.
- Transformer guard trace24 Dec 2024US 12,176,285 B2Texas Instruments Incorporated
- Semiconductor device having second connector that overlaps a part of first connector27 Jun 2023US 11,688,711 B2Kabushiki Kaisha Toshiba
- Semiconductor package having a chip carrier and a metal plate sized independently of the chip carrier13 Jun 2023US 11,676,879 B2Infineon Technologies AG
- Semiconductor package and method for forming the same17 Sep 2026US 2026/0282906 A1STATS ChipPAC Management Pte. Ltd.
- Semiconductor device and vehicle3 Sep 2026US 2026/0262497 A1Rohm Co., Ltd.
- Molded packages with attached connectors12 Mar 2026US 2026/0076219 A1NXP USA, Inc.
- Transformer guard trace3 Apr 2025US 2025/0112148 A1
- Semiconductor device and power conversion apparatus30 Jan 2025US 2025/0038079 A1Mitsubishi Electric Corporation
Most cited
By later US patents
- Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby412US 6,423,570 B1Intel Corporation · 2002
- Pad array semiconductor device with thermal conductor and process for making the same386US 5,285,352 AMotorola, Inc. · 1994
- Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby382US 6,902,950 B2Intel Corporation · 2005
- Three dimensional integrated circuit package361US 5,016,138 A1991
- Semiconductor device having dual electrical contact sites344US 5,157,480 AMotorola, Inc. · 1992