H10W 72/823
Interconnections through encapsulations
Official title: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
H10W72/823 (Interconnections through encapsulations) appears on 1,928 US grants and 2,779 published applications in this corpus.
Search patents in H10W- Granted patents
- 1,928
- Published applications
- 2,779
- Assignees
- 292
- Inventors
- 3,085
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2000 | 1 | 0 |
| 2001 | 0 | 0 |
| 2002 | 1 | 1 |
| 2003 | 0 | 1 |
| 2004 | 1 | 2 |
| 2005 | 0 | 4 |
| 2006 | 1 | 6 |
| 2007 | 3 | 7 |
| 2008 | 1 | 5 |
| 2009 | 4 | 9 |
| 2010 | 12 | 14 |
| 2011 | 12 | 35 |
| 2012 | 19 | 69 |
| 2013 | 39 | 75 |
| 2014 | 55 | 84 |
| 2015 | 83 | 127 |
| 2016 | 151 | 146 |
| 2017 | 175 | 181 |
| 2018 | 161 | 201 |
| 2019 | 158 | 143 |
| 2020 | 145 | 157 |
| 2021 | 114 | 183 |
| 2022 | 141 | 238 |
| 2023 | 163 | 284 |
| 2024 | 172 | 258 |
| 2025 | 191 | 240 |
| 2026 | 125 | 309 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor package and manufacturing method of semiconductor package6 Oct 2026US 12,757,758 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Multiple plated via arrays of different wire heights on a same substrate6 Oct 2026US RE51,062 E1Adeia Semiconductor Technologies LLC
- Device, method, and system to mitigate warpage of a composite chiplet22 Sep 2026US 12,745,642 B2Intel Corporation
- Semiconductor structure with integrated passive device having opposed solder bumps22 Sep 2026US 12,745,672 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Silicon nitride liner for promotion of mold adhesion in integrated circuits15 Sep 2026US 12,740,475 B2Intel Corporation
- Semiconductor package8 Oct 2026US 2026/0314404 A1Samsung Electronics Co., Ltd.
- Semiconductor package with stacked members8 Oct 2026US 2026/0314415 A1Samsung Electronics Co., Ltd.
- Circuit package structure with a conductive pillar and related conductive pillar1 Oct 2026US 2026/0305355 A1Chengdu Monolithic Power Systems Co., Ltd.
- Electronic package, manufacturing method thereof, electronic component, and manufacturing method thereof1 Oct 2026US 2026/0305375 A1Siliconware Precision Industries Co., Ltd.
- Semiconductor package1 Oct 2026US 2026/0305413 A1LG Innotek Co., Ltd.
Most cited
By later US patents
- Method of fabricating interconnect structure for package-on-package devices1,078US 9,048,222 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Package systems having interposers1,064US 9,048,233 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2015
- Discrete polymer in fan-out packages731US 9,666,502 B2Taiwan Semiconductor Manufacturing Company.Ltd · 2017
- Independent 3D stacking269US 9,559,081 B1Apple Inc. · 2017
- Wafer-to-wafer bonding structure256US 9,461,007 B2Samsung Electronics Co., Ltd. · 2016