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US 12,740,475 B2Granted
Silicon nitride liner for promotion of mold adhesion in integrated circuits
AssigneeIntel Corporation
InventorsXavier Francois Brun, Jason M. Gamba, Srinivas V. Pietambaram
Life of this patent
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Abstract
An example an IC package including a liner for promotion of mold adhesion includes a conductive structure on a support surface; a mold material at least partially encasing the conductive structure; and a liner on a surface of the conductive structure between the surface of the conductive structure and the mold material, wherein the liner comprises a material including silicon and nitrogen.
Claims20
An integrated circuit (IC) package, comprising:
- a conductive structure over a surface;
- an IC die proximate the conductive structure and coupled to the surface, wherein the IC die has a first face facing the surface, a second face opposite the first face, and a side extending between the first face and the second face;
- an insulator material at least partially encasing the conductive structure;
- a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material, and wherein the first liner includes silicon and nitrogen;
- and,
- a second liner on the side of the IC die, wherein the second liner is between the side of the IC die and the insulator material.
3 more elements
A microelectronic assembly, comprising:
- a conductive structure comprising a conductive pillar;
- an IC die proximate the conductive structure, the IC die comprising first and second faces opposite one another, and further comprising sides extending between the first and second faces;
- an insulator material encasing at least a portion of the IC die and the conductive structure;
- a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material;
- and
- a second liner on the sides of the IC die, wherein the second liner is between the sides of the IC die and the insulator material,
- wherein the first and second liners include silicon and nitrogen.
4 more elements
A process of making a microelectronic assembly, the process comprising:
- providing a conductive structure comprising a pillar that includes copper;
- providing an IC die proximate the conductive structure, the IC die comprising first and second faces opposite one another, and further comprising sides extending between the first and second faces;
- providing an insulator material encasing at least a portion of the IC die and the conductive structure;
- providing a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material;
- and
- providing a second liner on the sides of the IC die, wherein the second liner is between the sides of the IC die and the insulator material;
- wherein the first and second liners include silicon and nitrogen.
4 more elements
An integrated circuit (IC) package, comprising:
- a conductive structure over a surface;
- an IC die proximate the conductive structure and coupled to the surface, wherein the IC die has a first face facing the surface, a second face opposite the first face, and a side extending between the first face and the second face;
- an insulator material at least partially encasing the conductive structure, wherein a portion of the insulator material is on at least a portion of the first face of the IC die;
- a first liner on a surface of the conductive structure, wherein the first liner is between the surface of the conductive structure and the insulator material, and wherein the first liner includes silicon and nitrogen;
- and
- a second liner on at least a portion of the surface, wherein the second liner is between the insulator material on the portion of the first face of the IC die and the portion of the surface.
3 more elements
Dependencies are inferred from the claim text.