H10P 95/11
Separation of active layers from substrates
Official title: {Separation of active layers from substrates}
H10P95/11 (Separation of active layers from substrates) appears on 711 US grants and 889 published applications in this corpus.
Search patents in H10P- Granted patents
- 711
- Published applications
- 889
- Assignees
- 306
- Inventors
- 1,504
- Latest grant
- 1 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 1 | 0 |
| 1997 | 2 | 0 |
| 1998 | 3 | 0 |
| 1999 | 4 | 0 |
| 2000 | 12 | 0 |
| 2001 | 5 | 1 |
| 2002 | 4 | 6 |
| 2003 | 7 | 0 |
| 2004 | 2 | 2 |
| 2005 | 0 | 3 |
| 2006 | 0 | 7 |
| 2007 | 3 | 7 |
| 2008 | 6 | 4 |
| 2009 | 2 | 10 |
| 2010 | 8 | 11 |
| 2011 | 5 | 9 |
| 2012 | 4 | 13 |
| 2013 | 14 | 24 |
| 2014 | 19 | 31 |
| 2015 | 38 | 39 |
| 2016 | 36 | 33 |
| 2017 | 40 | 56 |
| 2018 | 40 | 64 |
| 2019 | 62 | 56 |
| 2020 | 53 | 76 |
| 2021 | 53 | 77 |
| 2022 | 52 | 99 |
| 2023 | 64 | 100 |
| 2024 | 69 | 69 |
| 2025 | 69 | 58 |
| 2026 | 33 | 34 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Semiconductor device and method of forming sacrificial heteroepitaxy interface to provide substantially defect-free silicon carbide substrate1 Sep 2026US 12,727,450 B2Icemos Technology Ltd.
- Display apparatus and electronic device25 Aug 2026US 12,720,915 B2Semiconductor Energy Laboratory Co.Ltd.
- Chip bonding system and chip bonding method25 Aug 2026US 12,721,104 B2Bondtech Co., Ltd.
- Semiconductor device and semiconductor manufacturing method thereof18 Aug 2026US 12,713,855 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Coupon wafer and method of preparation thereof14 Jul 2026US 12,681,236 B2Rockley Photonics Limited
- Vertical transistors occupying reduced chip area and the methods forming the same17 Sep 2026US 2026/0282881 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Methods for the provision of a coated graphene layer structure on a silicon-containing wafer20 Aug 2026US 2026/0247936 A1Paragraf Limited
- Carrier structure and methods of forming the same20 Aug 2026US 2026/0248043 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Method for producing semiconductor device and laminated body for temporary fixing6 Aug 2026US 2026/0226320 A1Resonac Corporation
- Method for producing led mounting substrate, cleaning solution, and cleaning method6 Aug 2026US 2026/0231711 A1Shin-Etsu Chemical Co., Ltd.
Most cited
By later US patents
- Method for fabricating self-assembling microstructures513US 5,545,291 AThe Regents of the University of California · 1996
- Controlled cleavage process and device for patterned films426US 5,985,742 ASilicon Genesis Corporation · 1999
- Apparatus for fabricating self-assembling microstructures356US 5,904,545 AThe Regents of the University of California · 1999
- Low temperature semiconductor layering and three-dimensional electronic circuits using the layering351US 6,600,173 B2Cornell Research Foundation, Inc. · 2003
- Controlled cleavage process and device for patterned films344US 6,528,391 B1Silicon Genesis Corporation · 2003