Vertical transistors occupying reduced chip area and the methods forming the same

A structure comprising:

• a first vertical transistor comprising:
• a first vertical channel;
• and
• a first gate electrode encircling the first vertical channel;
• a second vertical transistor comprising:
• a second vertical channel;
• and
• a second gate electrode encircling the second vertical channel;

A structure comprising:

• a dielectric layer;
• a transistor comprising:
• a vertical channel;
• a gate dielectric, wherein in a cross-section of the structure, the gate dielectric comprises opposing portions on opposing sides of the vertical channel;
• a gate electrode, wherein the gate dielectric is between the vertical channel and the gate electrode, and wherein the vertical channel, the gate dielectric, and the gate electrode are in the dielectric layer;
• a first source/drain region connected to a top end of the vertical channel;
• and
• a second source/drain region connected to a bottom end of the vertical channel;
• and
• a power supplying path comprising:
• a first portion higher than the transistor;
• a second portion penetrating through the dielectric layer;
• and
• a third portion lower than the transistor, wherein the power supplying path is electrically coupled to the second source/drain region.