H10P 90/191
Using full isolation by porous oxide silicon [fipos]
Official title: {using full isolation by porous oxide silicon [FIPOS]}
H10P90/191 (Using full isolation by porous oxide silicon [fipos]) appears on 65 US grants and 36 published applications in this corpus.
Search patents in H10P- Granted patents
- 65
- Published applications
- 36
- Assignees
- 48
- Inventors
- 142
- Latest grant
- 1 Jul 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 2 | 0 |
| 1978 | 2 | 0 |
| 1979 | 1 | 0 |
| 1980 | 1 | 0 |
| 1981 | 1 | 0 |
| 1982 | 0 | 0 |
| 1983 | 2 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 5 | 0 |
| 1990 | 1 | 0 |
| 1991 | 2 | 0 |
| 1992 | 4 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 2 | 0 |
| 1999 | 2 | 0 |
| 2000 | 0 | 0 |
| 2001 | 2 | 0 |
| 2002 | 2 | 0 |
| 2003 | 0 | 3 |
| 2004 | 1 | 2 |
| 2005 | 1 | 2 |
| 2006 | 3 | 1 |
| 2007 | 0 | 2 |
| 2008 | 0 | 2 |
| 2009 | 2 | 3 |
| 2010 | 3 | 2 |
| 2011 | 1 | 0 |
| 2012 | 1 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 1 | 1 |
| 2017 | 0 | 1 |
| 2018 | 1 | 2 |
| 2019 | 3 | 2 |
| 2020 | 2 | 2 |
| 2021 | 2 | 4 |
| 2022 | 1 | 1 |
| 2023 | 1 | 2 |
| 2024 | 2 | 1 |
| 2025 | 1 | 0 |
| 2026 | 0 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method for forming a semiconductor structure having a porous semiconductor layer in RF devices1 Jul 2025US 12,347,673 B2Newport Fab, LLC
- RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation22 Oct 2024US 12,125,739 B2Qorvo US, Inc.
- RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation23 Jul 2024US 12,046,505 B2Qorvo US, Inc.
- Method of forming semiconductor-on-insulator (SOI) substrate25 Jul 2023US 11,710,656 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor structure with partially embedded insulation region and related method11 Oct 2022US 11,469,136 B2STMicroelectronics S,r.l.
- Systems and methods for tuning porous bandgaps to reduce thermal donor effects20 Aug 2026US 2026/0247673 A1IQE plc
- Systems and methods for porous backside contacts16 Jul 2026US 2026/0206313 A1IQE plc
- Systems and methods for stress reduction in porous layers12 Mar 2026US 2026/0076113 A1IQE plc
- Compound semiconductor layered structure and process for preparing the same18 Apr 2024US 2024/0128080 A1Umicore AG & Co. KG
- Rf devices with enhanced performance and methods of forming the same utilizing localized soi formation25 May 2023US 2023/0163021 A1Qorvo US, Inc.
Most cited
By later US patents
- Formation of SOI by oxidation of silicon with engineered porosity gradient200US 7,772,096 B2International Machines Corporation · 2010
- Process for production of semiconductor substrate109US 5,856,229 ACanon Kabushiki Kaisha · 1999
- Method for preparing semiconductor member89US 5,840,616 ACanon Kabushiki Kaisha · 1998
- Method of making silicon-on-porous-silicon by ion implantation72US 5,387,541 AThe Secretary for Defence in Her Britannic Majesty's Government of the United Kingdom of Great Britain and Northern Ireland · 1995
- Annealed porous silicon with epitaxial layer for SOI70US 6,376,285 B1Texas Instruments Incorporated · 2002