H10D 30/6727
Having source or drain regions connected to bulk conducting substrates
Official title: {having source or drain regions connected to bulk conducting substrates}
H10D30/6727 (Having source or drain regions connected to bulk conducting substrates) appears on 154 US grants and 145 published applications in this corpus.
Search patents in H10D- Granted patents
- 154
- Published applications
- 145
- Assignees
- 77
- Inventors
- 250
- Latest grant
- 8 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1988 | 1 | 0 |
| 1989 | 2 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 3 | 0 |
| 1995 | 1 | 0 |
| 1996 | 2 | 0 |
| 1997 | 3 | 0 |
| 1998 | 0 | 0 |
| 1999 | 4 | 0 |
| 2000 | 2 | 0 |
| 2001 | 2 | 2 |
| 2002 | 5 | 2 |
| 2003 | 9 | 11 |
| 2004 | 1 | 12 |
| 2005 | 9 | 12 |
| 2006 | 13 | 11 |
| 2007 | 12 | 16 |
| 2008 | 8 | 12 |
| 2009 | 9 | 5 |
| 2010 | 5 | 4 |
| 2011 | 4 | 4 |
| 2012 | 2 | 3 |
| 2013 | 3 | 0 |
| 2014 | 4 | 1 |
| 2015 | 1 | 0 |
| 2016 | 5 | 4 |
| 2017 | 0 | 2 |
| 2018 | 2 | 4 |
| 2019 | 2 | 8 |
| 2020 | 6 | 10 |
| 2021 | 10 | 8 |
| 2022 | 7 | 4 |
| 2023 | 5 | 3 |
| 2024 | 4 | 4 |
| 2025 | 4 | 2 |
| 2026 | 2 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Complementary transistor and semiconductor device8 Sep 2026US 12,733,254 B2Sony Group Corporation
- Methods to process 3D semiconductor devices and structures which have metal layers16 Jun 2026US 12,660,326 B2Monolithic 3D Inc.
- 3D semiconductor devices and structures with metal layers29 Jul 2025US 12,376,382 B2Monolithic 3D Inc.
- Transistor level interconnection methodologies utilizing 3D interconnects8 Apr 2025US 12,272,730 B2Adeia Semiconductor Inc.
- Source contact formation of MOSFET with gate shield buffer for pitch reduction18 Feb 2025US 12,230,707 B2Silanna Asia Pte Ltd
- Methods to process 3d semiconductor devices and structures which have metal layers12 Mar 2026US 2026/0075952 A1Monolithic 3D Inc.
- Transistor level interconnection methodologies utilizing 3d interconnects19 Jun 2025US 2025/0204006 A1Adeia Semiconductor Inc.
- 3d semiconductor devices and structures with metal layers20 Mar 2025US 2025/0098325 A1Monolithic 3D Inc.
- 3d semiconductor devices and structures with metal layers12 Sep 2024US 2024/0304617 A1Monolithic 3D Inc.
- 3d semiconductor devices and structures with metal layers4 Jul 2024US 2024/0222368 A1Monolithic 3D Inc.
Most cited
By later US patents
- Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same171US 6,483,171 B1Micron Technology, Inc. · 2002
- Transistor level interconnection methodologies utilizing 3D interconnects162US 10,991,804 B2Xcelsis Corporation · 2021
- Thin-film SOI semiconductor device having heavily doped diffusion regions beneath the channels of transistors159US 5,294,821 ASeiko Epson Corporation · 1994
- SOI wafer device and a method of fabricating the same86US 6,407,427 B1Hyundai Electronics Industries Co., Ltd. · 2002
- Process for manufacturing a semiconductor device by applying a non-single-crystalline material on a sidewall inside of an opening portion for growing a single-crystalline semiconductor body78US 5,612,230 ACanon Kabushiki Kaisha · 1997