Methods to process 3D semiconductor devices and structures which have metal layers

A method to process a semiconductor device, the method comprising:

• providing a substrate;
• processing said substrate to form a first level comprising a first single crystal silicon layer and a plurality of first transistors;
• forming a first metal layer;
• forming a second metal layer,
• wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
• processing a second level comprising a plurality of second transistors;
• processing a third level comprising a plurality of third transistors,
• wherein said third level is disposed over said second level;
• forming a third metal layer disposed over said third level;
• forming a fourth metal layer disposed over said third metal layer;
• processing a fourth level comprising a second single crystal silicon layer,
• wherein said fourth level is disposed over said fourth metal layer,
• wherein each of said plurality of second transistors comprises a metal gate, and
• wherein said second metal layer comprises a power delivery network;
• and
• forming a via disposed through said second level and through said third level,
• wherein each of said plurality of third transistors comprises a metal gate,
• wherein said second level comprises a first array of memory cells,
• wherein said third level comprises a second array of memory cells,
• wherein formation of said plurality of second transistors comprises a first lithography step,
• wherein formation of said plurality of third transistors comprises a second lithography step,
• wherein said first level comprises input and output (“IO”) circuits,
• wherein connections of said device to external devices comprises said input and output (“IO”) circuits, and
• wherein said second level is disposed over said first level;
• processing a connection path from said third metal layer to said second metal layer, wherein said connection path comprises said via.

A method to process a semiconductor device, the method comprising:

• providing a substrate;
• processing said substrate to form a first level comprising a first single crystal silicon layer and a plurality of first transistors;
• forming a first metal layer;
• forming a second metal layer,
• wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
• processing a second level comprising a plurality of second transistors;
• processing a third level comprising a plurality of third transistors,
• wherein said third level is disposed over said second level;
• forming a third metal layer disposed over said third level;
• forming a fourth metal layer disposed over said third metal layer;
• processing a fourth level comprising a second single crystal silicon layer,
• wherein said fourth level is disposed over said fourth metal layer,
• wherein each of said plurality of second transistors comprises a metal gate, and
• wherein said second metal layer comprises a power delivery network;
• and
• forming a via disposed through said second level and through said third level,
• wherein each of said plurality of third transistors comprises a metal gate,
• wherein said second level comprises a first array of memory cells,
• wherein said third level comprises a second array of memory cells, and
• wherein said first level comprises power control circuits controlling power delivery to said second transistors,
• wherein said power control circuits comprise a portion of said plurality of said first transistors, and
• wherein said second level is disposed over said first level;
• processing a power delivery to at least one of said plurality of second transistors, wherein said power delivery path comprises at least a part of said second metal layer.