Complementary transistor and semiconductor device
AssigneeSony Group Corporation
InventorsHidetoshi Oishi, Koichi Matsumoto, Kazuyuki Tomida
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Abstract
A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211, 212 respectively.
Claims20
A complementary transistor, comprising:
- a first transistor including:
- a first control electrode;
- and
- a first active region located below the first control electrode and formed by layering a first A layer and a first B layer;
- and
- a second transistor including:
- a second control electrode;
- and
- a second active region located below the second control electrode formed by layering a second A layer and a second B layer,
- wherein the first B layer is constituted of a two-dimensional material or graphene, and the second B layer is constituted of a two-dimensional material or graphene.
A complementary transistor, comprising:
- a semiconductor substrate;
- a first transistor including:
- a first control electrode;
- and
- a first active region located below the first control electrode and formed by layering a first A layer and a first B layer;
- and
- a second transistor including:
- a second control electrode;
- and
- a second active region located below the second control electrode formed by layering a second A layer and a second B layer,
- wherein the first B layer is constituted of a two-dimensional material or graphene, and the second B layer is constituted of a two-dimensional material or graphene.
A complementary transistor, comprising:
- a semiconductor substrate;
- a first transistor including:
- a first control electrode;
- and
- a first active region located below the first control electrode and formed by layering a first A layer and a first B layer;
- a second transistor including:
- a second control electrode;
- and
- a second active region located below the second control electrode formed by layering a second A layer and a second B layer;
- and
- a buffer layer provided between the first control electrode and the semiconductor substrate.
Dependencies are inferred from the claim text.