Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
AssigneeMicron Technology, Inc.
InventorsLeonard Forbes, Wendell P. Noble, Alan R. Reinberg
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Abstract
A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.
Claims16
An integrated circuit structure, comprising:
- a silicon substrate having a higher order crystal plane;
- and
- NMOS and PMOS transistors formed vertically on said higher order crystal plane of said silicon substrate, wherein each of said NMOS and PMOS transistors have at least two active regions that are aligned vertically to one another and with respect to said silicon substrate and are separated from each other by a conduction region;
- each said conduction region of said NMOS and PMOS transistors comprise channels lying vertically in the (110) plane or higher.
A processor-based system comprising:
- a processor;
- a memory device coupled to said processor, said memory device comprising at least one memory circuit, said memory circuit comprising:
- a substrate having a higher order crystal orientation;
- and
- at least one pair of vertical NMOS and PMOS transistors formed as a CMOS transistor pair fabricated on said higher order crystal orientation, wherein each of said vertical NMOS and PMOS transistors comprise at least two active areas separated by a channel region, said active areas and channel region being in a vertical column in relation to said substrate for each said transistor and said channel region lying vertically in the (110) plane or higher;
- and
- a storage device coupled to said CMOS transistor pair.
A method of operating a CMOS circuit comprising:
- providing an integrated circuit having PMOS and NMOS transistors fabricated vertically in a higher order surface of a silicon wafer;
- each of said PMOS and NMOS transistors comprising source and drain regions so that the source of each said transistors is aligned vertically with respect to the drain of the same transistor and is separated from said drain of the transistor by a conduction area, said conduction are having a channel region with sidewalls in the (110) plane or higher;
- and
- biasing said transistors to operate in velocity saturation.
A memory circuit comprising:
- at least one pair of vertical NMOS and PMOS transistors formed as a CMOS transistor pair on a higher order surface of a silicon substrate with source and drain regions of each of said transistors aligned vertically relative to each other and each of said transistors having a channel region with sidewalls in the (110) plane or higher, wherein said at least one pair of transistors is in electrical connection with at least one memory cell.
A processor-based system comprising:
- a processor;
- a memory device coupled to said processor, said memory device comprising at least one memory circuit, said memory circuit comprising:
- a substrate having a higher order crystal orientation;
- and
- at least one pair of vertical NMOS and PMOS transistors formed as a CMOS transistor pair fabricated on said higher order crystal orientation, said vertical NMOS and PMOS transistors each comprising at least three vertically oriented layers, two being active areas separated by the third layer being a conductive layer, wherein said at least three layers have vertical sidewalls in the plane of (110) crystal orientation or higher;
- and
- a storage device coupled to said CMOS transistor pair.
Dependencies are inferred from the claim text.