3D semiconductor devices and structures with metal layers

A semiconductor device, the semiconductor device comprising:

• a first level comprising a first single crystal silicon layer and a plurality of first transistors;
• a first metal layer;
• a second metal layer,
• wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
• a second level comprising a plurality of second transistors, said second level disposed over said first level;
• a third level comprising a plurality of third transistors, said third level disposed over said second level;
• a third metal layer disposed over said third level;
• a fourth metal layer disposed over said third metal layer;
• and
• a via disposed through said second level and through said third level as part of a connection path between said third metal layer to said second metal layer,
• wherein each of said plurality of second transistors comprises a metal gate,
• wherein at least one of said metal gates comprises tungsten,
• wherein said second level comprises a first array of memory cells,
• wherein said third level comprises a second array of memory cells,
• wherein formation of said plurality of second transistors comprises a first lithography step, and
• wherein formation of said plurality of third transistors comprises a second lithography step.

A semiconductor device, the semiconductor device comprising:

• a first level comprising a first single crystal silicon layer and a plurality of first transistors;
• a first metal layer;
• a second metal layer,
• wherein interconnection of said plurality of first transistors comprises said first metal layer and said second metal layer;
• a second level comprising a plurality of second transistors, said second level disposed over said first level;
• a third level comprising a plurality of third transistors, said third level disposed over said second level;
• a third metal layer disposed over said third level;
• a fourth metal layer disposed over said third metal layer;
• a fourth level comprising a second single crystal silicon layer,
• wherein said fourth level is disposed over said fourth metal layer,
• wherein each of said plurality of second transistors comprises a metal gate,
• wherein said second metal layer comprises a power delivery network;
• and
• a via disposed through said second level and through said third level,
• wherein each of said plurality of third transistors comprises a metal gate,
• wherein said second level comprises a first array of memory cells,
• wherein said third level comprises a second array of memory cells,
• wherein said first level comprises power control circuits controlling power delivery to said second transistors, and
• wherein said power control circuits comprise a portion of said plurality of said first transistors.