H10D 10/054
Forming extrinsic base regions on silicon substrate after insulating device isolation in
Official title: {Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions}
H10D10/054 (Forming extrinsic base regions on silicon substrate after insulating device isolation in) appears on 364 US grants and 224 published applications in this corpus.
Search patents in H10D- Granted patents
- 364
- Published applications
- 224
- Assignees
- 109
- Inventors
- 535
- Latest grant
- 15 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 1 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 2 | 0 |
| 1984 | 2 | 0 |
| 1985 | 3 | 0 |
| 1986 | 0 | 0 |
| 1987 | 3 | 0 |
| 1988 | 2 | 0 |
| 1989 | 4 | 0 |
| 1990 | 3 | 0 |
| 1991 | 5 | 0 |
| 1992 | 11 | 0 |
| 1993 | 16 | 0 |
| 1994 | 13 | 0 |
| 1995 | 13 | 0 |
| 1996 | 9 | 0 |
| 1997 | 5 | 0 |
| 1998 | 6 | 0 |
| 1999 | 6 | 0 |
| 2000 | 12 | 0 |
| 2001 | 10 | 7 |
| 2002 | 21 | 22 |
| 2003 | 15 | 9 |
| 2004 | 21 | 20 |
| 2005 | 26 | 27 |
| 2006 | 18 | 15 |
| 2007 | 16 | 13 |
| 2008 | 6 | 5 |
| 2009 | 11 | 6 |
| 2010 | 9 | 3 |
| 2011 | 9 | 11 |
| 2012 | 4 | 5 |
| 2013 | 10 | 9 |
| 2014 | 8 | 11 |
| 2015 | 10 | 6 |
| 2016 | 9 | 10 |
| 2017 | 5 | 2 |
| 2018 | 7 | 9 |
| 2019 | 7 | 5 |
| 2020 | 3 | 3 |
| 2021 | 5 | 6 |
| 2022 | 5 | 4 |
| 2023 | 7 | 6 |
| 2024 | 4 | 2 |
| 2025 | 1 | 5 |
| 2026 | 1 | 3 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Bipolar transistor structures with cavity below extrinsic base and methods to form same15 Sep 2026US 12,740,113 B2GLOBALFOUNDRIES U. S. Inc.
- Separate epitaxy layers for nanowire stack GAA device8 Jul 2025US 12,356,667 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Bipolar transistor structure on semiconductor fin and methods to form same24 Dec 2024US 12,176,426 B2GLOBALFOUNDRIES U. S. Inc.
- Darlington pair bipolar junction transistor sensor26 Nov 2024US 12,154,899 B2International Business Machines Corporation
- Bipolar transistor27 Feb 2024US 11,916,135 B2GLOBALFOUNDRIES U. S. Inc.
- Method of manufacturing an electronic device6 Aug 2026US 2026/0231450 A1STMicroelectronics International N. V.
- Compact esd structure25 Jun 2026US 2026/0181925 A1Qorvo US, Inc.
- Method for manufacturing an electronic device18 Jun 2026US 2026/0173418 A1STMicroelectronics International N. V.
- Bipolar transistor structures with sloped base sidewalls and related methods25 Dec 2025US 2025/0393226 A1GLOBALFOUNDRIES U. S. Inc.
- Separate Epitaxy Layers for Nanowire Stack GAA Device17 Apr 2025US 2025/0126842 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers135US 4,663,831 AMotorola, Inc. · 1987
- Method of manufacturing semiconductor device124US 5,227,329 AHitachi, Ltd. · 1993
- Trenched bipolar transistor structures111US 5,311,055 AThe United States of America as represented by the Secretary of the Navy · 1994
- Diffused extrinsic base and method for fabrication95US 6,900,519 B2International Business Machines Corporation · 2005
- Method for producing a laterally limited single-crystal region with selective epitaxy and the employment thereof for manufacturing a bipolar transistor as well as a MOS transistor85US 5,432,120 ASiemens Aktiengesellschaft · 1995