Separate epitaxy layers for nanowire stack GAA device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
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Abstract
The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
Claims20
An integrated circuit, comprising:
- a substrate including a first substrate region;
- a first plurality of strips of a first semiconductor material over the first substrate region;
- a semiconductor base layer between the first plurality of strips and the substrate, the semiconductor base layer having a flat upper surface;
- a first gate structure surrounding at least a first strip of the first plurality of strips, the semiconductor base layer being distinct from the first gate structure;
- an isolation region along opposing sides of the semiconductor base layer;
- and
- a first source/drain structure contacting the first plurality of strips.
An integrated circuit, comprising:
- a substrate, the substrate comprising a first semiconductor material;
- a base layer in a recess in the substrate, wherein the base layer comprises a first layer, wherein the first layer is a second semiconductor material different than the first semiconductor material;
- and
- a plurality of semiconductor strips over the base layer;
- a gate structure surrounding the plurality of semiconductor strips, the base layer being different from the gate structure;
- and
- a source/drain structure contacting the plurality of semiconductor strips.
An integrated circuit, comprising:
- a substrate having a first region and a second region, the substrate comprising a first semiconductor material;
- a base layer embedded in a recess in the first region, wherein the second region is free of the base layer;
- a dielectric layer extending through the base layer;
- a plurality of first semiconductor layers over the substrate in the first region, the plurality of first semiconductor layers comprising a second semiconductor material;
- a first source/drain regions and a second source/drain region over the base layer in the first region, the first source/drain region and the second source/drain region being on opposing sides of the plurality of first semiconductor layers;
- a first gate structure over the plurality of first semiconductor layers, wherein the first gate structure extends between adjacent layers of the plurality of first semiconductor layers, wherein the first gate structure is above an upper surface of the base layer;
- a plurality of second semiconductor layers over the substrate in the second region, the plurality of second semiconductor layers comprising a third semiconductor material different from the second semiconductor material;
- a third source/drain region and a fourth source/drain region over the substrate in the second region, the third source/drain region and the fourth source/drain region being on opposing sides of the plurality of second semiconductor layers;
- and
- a second gate structure over the plurality of second semiconductor layers, wherein the second gate structure extends between adjacent layers of the plurality of second semiconductor layers.
Dependencies are inferred from the claim text.