H10B 20/40
Having the source region and drain region on different levels
Official title: {having the source region and drain region on different levels, e.g. vertical channel}
H10B20/40 (Having the source region and drain region on different levels) appears on 101 US grants and 62 published applications in this corpus.
Search patents in H10B- Granted patents
- 101
- Published applications
- 62
- Assignees
- 36
- Inventors
- 139
- Latest grant
- 5 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1980 | 2 | 0 |
| 1981 | 2 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 2 | 0 |
| 1995 | 3 | 0 |
| 1996 | 1 | 0 |
| 1997 | 1 | 0 |
| 1998 | 1 | 0 |
| 1999 | 4 | 0 |
| 2000 | 3 | 0 |
| 2001 | 5 | 1 |
| 2002 | 3 | 0 |
| 2003 | 1 | 0 |
| 2004 | 1 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 0 |
| 2008 | 0 | 0 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 2 |
| 2015 | 1 | 3 |
| 2016 | 4 | 2 |
| 2017 | 8 | 9 |
| 2018 | 13 | 10 |
| 2019 | 6 | 8 |
| 2020 | 12 | 9 |
| 2021 | 6 | 6 |
| 2022 | 6 | 4 |
| 2023 | 3 | 2 |
| 2024 | 1 | 2 |
| 2025 | 4 | 2 |
| 2026 | 2 | 2 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Semiconductor device and method of manufacturing the semiconductor device5 May 2026US 12,621,988 B2SK hynix Inc.
- Read-only memory method, layout, and device17 Mar 2026US 12,580,033 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method for manufacturing fully self-aligned high-density 3D multi-layer memory2 Sep 2025US 12,408,334 B2Chengdu Pbm Technology Ltd.
- Microelectronic devices with isolation trenches in upper portions of tiered stacks, and related methods22 Jul 2025US 12,369,333 B2
- Read-only memory with vertical transistors20 May 2025US 12,310,009 B2International Business Machines Corporation
- Semiconductor device and method of manufacturing the semiconductor device10 Sep 2026US 2026/0271281 A1SK hynix Inc.
- Read-only memory method, layout, and device2 Jul 2026US 2026/0188400 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Microelectronic devices with pillars extending through upper and lower tiered stack structures and an intermediate dielectric region13 Nov 2025US 2025/0351381 A1Lodestar Licencing Group LLC
- Read-only memory method, layout, and device9 Jan 2025US 2025/0014659 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Microelectronic devices with isolation trenches in upper portions of tiered stacks, and related methods25 Jul 2024US 2024/0251570 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Memory cell arrangement with vertical MOS transistors and the production process thereof532US 6,180,979 B2Siemens Aktiengesellschaft · 2001
- Memory cell configuration and method for its fabrication185US 5,994,746 ASiemens Aktiengesellschaft · 1999
- Method for making self-aligned source/drain mask ROM memory cell using trench etched channel105US 5,595,927 ATaiwan Semiconductor Manufacturing Company.Ltd · 1997
- Semiconductor device and method of producing same87US 5,057,896 AFujitsu Limited · 1991
- Method for fabricating a type of trench mask ROM cell81US 6,303,436 B1Mosel Vitelic, Inc. · 2001