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US 5,994,746 AGranted
Memory cell configuration and method for its fabrication
AssigneeSiemens Aktiengesellschaft
InventorsHans Reisinger, Reinhard Stengl, Franz Hofmann, Wolfgang Krautschneider, Josef Willer
Life of this patent
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Abstract
The memory cell has transistors that are arranged three-dimensionally. Vertical MOS transistors are arranged on the sidewalls of semiconductor webs, and a plurality of transistors are arranged one above the other on each sidewall. The transistors that are arranged one above the other on a sidewall are connected in series.
Claims13
A memory cell configuration, comprising:
- a semiconductor substrate having a main surface;
- a plurality of webs disposed on and projecting above said main surface of said semiconductor substrate;
- each of said webs being formed of a stack of doped layers with mutually adjacent layers having respectively opposite conductivity type doping, said stack having sidewalls;
- three adjacent doped layers forming two source/drain regions and a channel region of a transistor;
- a gate dielectric disposed on at least one sidewall of said stacks;
- word lines running transversely to said webs and adjoining said gate dielectric at said sidewalls of said stacks;
- bit lines formed by said doped layers acting as said source/drain regions;
- said stack containing a number of doped layers sufficient to form at least two transistors disposed one above the other and connected in series via a common doped layer defining a common source/drain region.
5 more elements
Dependencies are inferred from the claim text.