Read-only memory method, layout, and device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKu-Feng Lin, Chia-En Huang, Chieh Lee, Kazumasa Uno, Ching-Wei Wu
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Abstract
A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.
Claims20
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two;
- based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups;
- and
- storing an IC layout diagram including the logic patterns in a storage device.
A read-only memory (ROM) integrated circuit (IC) comprising:
- a column of NOR-type ROM bit cells aligned in a column direction, wherein each ROM bit cell comprises a fin field-effect transistor (FinFET) comprising:
- a gate structure extending perpendicular to the column direction;
- and
- source/drain (S/D) structures adjacent to the gate structure;
- a power supply line and a bit line, each extending in the column direction and overlying each gate structure and S/D structure of the column of ROM bit cells;
- and
- a plurality of isolation structures configured to divide the column of ROM bit cells into electrically isolated groups of ROM bit cells, wherein
- each pair of adjacent ROM bit cells within each group of ROM bit cells shares a corresponding S/D structure, and
- each group of ROM bit cells of the column of ROM bit cells comprises a total number of ROM bit cells greater than two.
A method of manufacturing a read-only memory (ROM) integrated circuit (IC), the method comprising:
- forming a column of NOR-type ROM bit cells aligned in a column direction, wherein the forming each ROM bit cell comprises forming a fin field-effect transistor (FinFET) by:
- constructing a gate structure extending perpendicular to the column direction;
- and
- forming source/drain (S/D) structures adjacent to the gate structure;
- forming a plurality of isolation structures configured to divide the column of ROM bit cells into electrically isolated groups of ROM bit cells;
- and
- constructing a power supply line and a bit line, each extending in the column direction and overlying each gate structure and S/D structure of the column of ROM bit cells, wherein
- each pair of adjacent ROM bit cells within each group of ROM bit cells shares a corresponding S/D structure, and
- each group of ROM bit cells of the column of ROM bit cells comprises a total number of ROM bit cells greater than two.
Dependencies are inferred from the claim text.